A flexible multi-channel high-resolution time-to-digital converter ASIC

IEEE Nuclear Science Symposium and Medical Imaging Conference

Volumn 2, Issue , 2000, Pages

  Mota, M ^a   Christiansen, J ^a   Debieux, S ^b   Ryjov, V ^a   Moreira, P ^a   Marchioro, A ^a  

^a CERN   (Switzerland)

^b Engineering School of Geneva   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA PROCESSING; DIGITAL SIGNAL PROCESSING; DRIFT CHAMBERS; INTERPOLATION; PHASE LOCKED LOOPS;

CLOCK MULTIPLICATION; CMOS TECHNOLOGY; DELAY LOCKED LOOP; DIGITAL PROCESSING LOGIC; TIME TO DIGITAL CONVERTER;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0034593607     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. M. Mota et al., "A high-resolution time interpolator based on a Delay Locked Loop and an RC delay line", IEEE Journal of Solid-State Circuits, vol. 34, no. 10, pp. 1360-1366, October 1999.
2. T. A. Gorbics, "A high-resolution multihit time to digital converter integrated circuit", IEEE Transactions on Nuclear Science, vol. 44, no. 3, pt. 1, pp.379-384, June 1997.
3. M. Mota et al., "A four channel, self-calibrating, high-resolution Time-to-Digital Converter", Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98), Lisbon, Portugal, September 1998.
4. P. Moreira et al., "A 1.25Gbit/s Serializer for LHC Data and Trigger Optical Links", Proceedings of the 5th Workshop on Electronics for LHC Experiments, Snowmass, Colorado, USA, September 1999.
5. J. Doenberg et al., "Full-Speed Testing of A/D Converters", IEEE Journal of Solid-State Circuits, vol. 19, no. 6, pp. 820-827, December 1984.
6. J. Christiansen et al., "A data driven high resolution Time-to-Digital Converter", Proceedings of the 6th Workshop on Electronics for LHC Experiments, Krakow, Poland, September 2000.