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Volumn , Issue , 2005, Pages 218-223

Self-refereed on-chip jitter measurement circuit using vernier oscillators

Author keywords

[No Author keywords available]

Indexed keywords

FINE RESOLUTION; JITTER DISTRIBUTION; JITTER MEASUREMENT; VERNIER OSCILLATOR;

EID: 26844552486     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (21)

References (11)
  • 1
    • 84861271428 scopus 로고    scopus 로고
    • "Time Interval Measurement System Incorporating a Linear Ramp Generation Circuit", US Patent 6,194,925, to Wavecrest Corp., Patent and Trademark Office, Washington, D.C.
    • C. Kimsal and J.B. Wilstrup, "Time Interval Measurement System Incorporating a Linear Ramp Generation Circuit", US Patent 6,194,925, to Wavecrest Corp., Patent and Trademark Office, Washington, D.C., 2001.
    • (2001)
    • Kimsal, C.1    Wilstrup, J.B.2
  • 2
    • 84861268403 scopus 로고    scopus 로고
    • "Apparatus and Method for Measuring Time Interval with Very High Resolution", US Patent 6,137,749, to LeCroy Corp., Patent and Trademark Office, Washington, D.C.
    • R. L. Sumner, "Apparatus and Method for Measuring Time Interval with Very High Resolution", US Patent 6,137,749, to LeCroy Corp., Patent and Trademark Office, Washington, D.C., 2000.
    • (2000)
    • Sumner, R.L.1
  • 4
    • 17144435893 scopus 로고    scopus 로고
    • A high resolution CMOS time-to-digital converter utilizing a vernier delay line
    • Feb.
    • P Dudek, S. Szczepanski, and J.V. Hatfield, "A High Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line", IEEE Transaction on Solid-State Circuits, vol.35, pp. 240-247, Feb., 2000.
    • (2000) IEEE Transaction on Solid-State Circuits , vol.35 , pp. 240-247
    • Dudek, P.1    Szczepanski, S.2    Hatfield, J.V.3
  • 5
    • 0033315398 scopus 로고    scopus 로고
    • BIST for phase-locked loops in digital applications
    • S. Sunter and A. Roy, "BIST for Phase-Locked Loops in Digital Applications", International Test Conference, pp. 532-540, 1999.
    • (1999) International Test Conference , pp. 532-540
    • Sunter, S.1    Roy, A.2
  • 6
    • 0036575437 scopus 로고    scopus 로고
    • Embedded timing analysis: A SoC infrastructure
    • May-June
    • S. Tabatabaei and A. Ivanov, "Embedded Timing Analysis: A SoC Infrastructure", IEEE Design & Test of Computers, Vol. 19, pp24-36, May-June, 2002.
    • (2002) IEEE Design & Test of Computers , vol.19 , pp. 24-36
    • Tabatabaei, S.1    Ivanov, A.2
  • 7
    • 1342308084 scopus 로고    scopus 로고
    • A jitter characterization system using a component-invariant vernier delay line
    • January
    • A.H. Chan, G.W. Robert, "A Jitter Characterization System Using a Component-Invariant Vernier Delay Line", IEEE Transaction on Very Large Scale Integration Systems, vol. 12, No. 1, January 2004.
    • (2004) IEEE Transaction on Very Large Scale Integration Systems , vol.12 , Issue.1
    • Chan, A.H.1    Robert, G.W.2
  • 8
  • 9
    • 84861271427 scopus 로고    scopus 로고
    • "All Digital Built-In Self-Test Circuit for Phase-Locked Loops", U.S. Patent 6,661,266 B1, Dec.
    • P. N. Variyam and H. Balachandran, "All Digital Built-In Self-Test Circuit for Phase-Locked Loops", U.S. Patent 6,661,266 B1, Dec. 2002.
    • (2002)
    • Variyam, P.N.1    Balachandran, H.2
  • 10
    • 84861270267 scopus 로고    scopus 로고
    • "Jitter Measurement System and Method", U.S. Patent 6,295, 315 B1, September
    • A. M. Frish and T. H. Rinderknecht, "Jitter Measurement System and Method", U.S. Patent 6,295, 315 B1, September 2001.
    • (2001)
    • Frish, A.M.1    Rinderknecht, T.H.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.