A new cycle-time-to-digital converter with two level conversion scheme

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 2160-2163

  Huang, Hong Yi ^a   Wu, Sheng Da ^b   Tsai, Yi Jui ^b  

^a NATIONAL TAIPEI UNIVERSITY   (Taiwan)

^b FU JEN CATHOLIC UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; PHASE MODULATION; READOUT SYSTEMS; SYNCHRONOUS MACHINERY;

DUAL DLL; VERNIER DELAY LINE (VDL);

POWER CONVERTERS;

EID: 34548846420     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378601     Document Type: Conference Paper

References (5)

1. P. Dudek, S. Szczepanski, and J. Hatfield, "A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line," IEEE J. Solid-State Circuits, vol. 35, pp. 240-247, Feb. 2000
2. E. Raisanen-Ruosalainen, T. Rahkonen and J. Kostamovaara , "An Integrated Time-to-Digital Converter with 30-ps Single-Shot Precision," IEEE J. Solid-State Circuits, vol. 35, pp. 1507-1510, Oct. 2000
3. C.-S. Hwang, P. Chen and H.-W. Tsao, "A High-Precision Time-to-Digital Converter Using a Two-Level Conversion Scheme," IEEE Trans. Nucl. Sci., vol. 51, pp. 1349-1352, Aug. 2004.
4. K. Karadamoglou, Nikolaos P. Paschalidis, "An 11-bit High-Resolution and Adjustable-Range CMOS Time-to-Digital Converter for Space Science Instruments," IEEE J. Solid-State Circuits, vol. 39, pp. 214-222, Jan. 2004
5. F. Bigongiari, R. Roncella, "A 250-ps Time-Resolution CMOS Multihit Time-to-Digital Converter for Nuclear Physics Experiments," IEEE Trans. Nucl. Sci., vol. 46, pp. 73-77, Apr. 19