An interpolating clock synthesizer

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 9, 1996, Pages 1295-1301

  Bazes, Mel ^a,b,c,d   Ashuri, Roni ^b,e   Knoll, Ernest ^b,f,g  

^a IEEE

^b INTEL CORPORATION   (Israel)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d UNIVERSITY OF CALIFORNIA   (United States)

^e TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

^f GHEORGHE ASACHI TECHNICAL UNIVERSITY OF IASI   (Romania)

^g Electronics Development Center   (Romania)

Author keywords

[No Author keywords available]

Indexed keywords

FREQUENCY MULTIPLYING CIRCUITS; FREQUENCY SYNTHESIZERS; INTERFACES (COMPUTER); INTERPOLATION; MICROPROCESSOR CHIPS; PHASE SHIFTERS;

DIGITAL DELAY INTERPOLATION; DIGITAL PRECISION PHASE DETECTOR; DYNAMICALLY SELECTABLE FREQUENCY MULTIPLES; INPUT/OUTPUT INTERFACE; INTERPOLATING CLOCK SYNTHESIZER (ICS); READ ONLY MEMORY BASED DIGITAL WAVEFORM SYNTHESIS; SYNCHRONOUS DELAY LINE;

TIMING CIRCUITS;

EID: 0030241075     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.535413     Document Type: Article

References (9)

1. I. Young et al., "A PLL clock generator with 5-110 MHz lock range for microprocessors," in ISSCC Dig. Tech. Papers, Feb. 1992, pp. 50-51.
2. J. Alvarez et al., "A wide-bandwidth low-power PLL for PowerPC™ microprocessors," IEEE J. Solid-State Circuits, vol. 30, no. 4, pp. 383-391, Apr. 1995.
3. A. Efendovich et al., "Multifrequency zero-jitter delay locked loop," IEEE J. Solid-State Circuits, vol. 29, no. 1, pp. 67-70, Jan. 1994.
4. M. Horowitz et al., "PLL design for a 500 MB/s interface," in ISSCC Dig. Tech. Papers, Feb. 1993, pp. 160-161.
5. J. Dunning et al., "An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors," IEEE J. Solid-State Circuits, vol. 30, no. 4, pp. 412-442, Apr. 1995.
6. M. Bazes, "Method and apparatus for synthesizing digital waveforms," U.S. Patent no. 4 980 585, Dec. 1990.
7. M. Bazes and R. Ashuri, "A novel CMOS digital clock and data decoder," IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1934-1940, Dec. 1992.
8. M. Bazes, "A novel precision MOS synchronous delay line," IEEE J. Solid-State Circuits, vol. SC-20, no. 6, pp. 1265-1271, Dec. 1985.
9. M. Bohr et al., "A high performance 0.35 μm logic technology for 3.3 V and 2.5 V operation," in IEDM Tech. Dig., Dec. 1994, pp. 10.2.1-10.2.4.