A high-resolution time digitizer utilizing dual PLL circuits

IEEE Nuclear Science Symposium Conference Record

Volumn 2, Issue , 2004, Pages 969-973

  Arai, Yasuo ^a  

^a INSTITUTE OF PARTICLE AND NUCLEAR STUDIES   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; DRIFT CHAMBERS; ELECTRIC POTENTIAL; OPTICAL RESOLVING POWER; THERMAL EFFECTS;

COARSE TIMES; DELAY TIME; REFERENCE TIME; TIME-TO-DIGITAL CONVERTER (TDC);

PHASE LOCKED LOOPS;

EID: 23844491865     PISSN: 10957863     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. Y. Arai and T. Baba; "A CMOS Time to Digital Converter VLSI for High-Energy Physics", 1988 Symposium on VLSI Circuits, Tokyo, Aug. 22-24 1988, IEEE CAT. No. 88 TH 0227-9 Page 121.
2. Y. Arai and T. Matsumura and K. Endo: "A CMOS 4 ch × 1 k Time Memory LSI with 1 ns/bit Resolution", IEEE J. of Solid-State Circuits, vol.27, no.3, Mar. 1992, pp. 359-364.
3. Y. Arai, "Development of Frontend Electronics and TDC LSI for the ATLAS MDT", 7th International Conference on Instrumentation for Colliding Beam Physics Hamamatsu, Nov. 15-19, 1999, Nucl. Instr. Meth. A. Vol. 453, pp. 365-371 (2000).
4. A. Mantyniemi, T. Rahkonen, J. Kostamovaara, "An Integrated 9-Channel Time Digitizer with 30ps Resolution", ISSCC Digest of Technical Papers, vol. 1, pp. 266-465, 2002.
5. M. Mota, and J. Christiansen, "A High-Resolution Time Interpolator Based on a Delay Looked Loop and an RC Delay Line", IEEE J. of Solid-State Circuits, vol. 34, no. 10, pp. 1360-1366, Oct. 1999.
6. P. Dudek, S. Szczepanski, and J. V. Hatfield, "A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line", IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 240-247, Feb. 2000.
7. Chorng-Sii Hwang, Poki Chen, and Hen-Wai Tsao, "A High-Precision Time-to-Digital Converter Using a Two-Level Conversion Scheme", IEEE Trans. Nucl. Sci., vol. 51, no. 4, pp. 1349-1352, Aug. 2004.