A self-calibrating delay-locked delay line with shunt-capacitor circuit scheme

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 2, 2004, Pages 384-387

  Baronti, Federico ^a   Lunardini, Diego ^a   Roncella, Roberto ^a   Saletti, Roberto ^a  

^a UNIVERSITY OF PISA   (Italy)

Author keywords

Calibration; Delay circuits; Delay lines; Delay lock loops; Nonlinearities

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; FEEDBACK; INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTING SILICON; STATISTICAL TESTS;

DELAY LOCK LOOPS; DIFFERENTIAL NONLINEARITY; HARDWARE CORRECTION TECHNIQUE; NONLINEARITY CALIBRATION TECHNIQUE; SHUNT CAPACITOR CIRCUIT SCHEME;

DELAY CIRCUITS;

EID: 1242308365     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.821773     Document Type: Article

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