Network-on-Chip design and synthesis outlook

Integration, the VLSI Journal

Volumn 41, Issue 3, 2008, Pages 340-359

  Atienza, David ^a,b   Angiolini, Federico ^a,c   Murali, Srinivasan ^a   Pullini, Antonio ^d   Benini, Luca ^c   De Micheli, Giovanni ^a  

^a EPFL   (Switzerland)

^b UNIVERSIDAD COMPLUTENSE DE MADRID   (Spain)

^c UNIVERSITY OF BOLOGNA   (Italy)

^d POLITECNICO DI TORINO   (Italy)

Author keywords

Design automation; Network on chip; System on chip; Wires

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; ENERGY EFFICIENCY; WIRE;

NETWORK ON CHIP; SYSTEM ON CHIP;

INTEGRATED CIRCUITS;

EID: 43049181319     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2007.12.002     Document Type: Article

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