Bounded arbitration algorithm for QoS-supported on-chip communication

CODES+ISSS 2006: Proceedings of the 4th International Conference on Hardware Software Codesign and System Synthesis

Volumn , Issue , 2006, Pages 76-81

  Al Faruque, Mohammad Abdullah ^a   Weiss, Gereon ^a   Henkel, Joerg ^a  

^a UNIVERSITY OF KARLSRUHE   (Germany)

Author keywords

Bounded arbitration algorithm; Networks on chips; Quality of services

Indexed keywords

ALGORITHMS; BANDWIDTH; CONSTRAINT THEORY; DATA COMPRESSION; QUALITY OF SERVICE; RESOURCE ALLOCATION;

BANDWIDTH UTILIZATION; BOUNDED ARBITRATION; SUPPORTED ON-CHIP COMMUNICATION; TRANSACTION LEVEL;

MULTIPROCESSING SYSTEMS;

EID: 34547217982     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1176254.1176275     Document Type: Conference Paper

References (16)

1. http://www.prodesigncad.com.
2. http://www.xvid.org/.
3. L. Benini and G. D. Micheli. Networks on chips: A new soc. paradigm. Proc. of IEEE Computer,35(1), 2002.
4. E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny. QNoC: QoS architecture and design process for network on chip. Special issue on Networks on Chip, The Journal of Systems Architecture.
5. W. Dally and B. Towles. Route packets, not wires: On-chip interconnection networks. Proc. of the Design, Automation conf. (DAC'01), June. 2001.
6. E. Rijpkema et. al. Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip. Proc. of the Design, Automation and Test in Europe conf. (DATE), March. 2003.
7. P. Guerrier and A. Greiner. A generic architecture for on-chip packet switched interconnections. Proc. of the Design, Automation and Test in Europe conf. (DATE), March. 2000.
8. M. D. Harmanci, N. P. Escudero, Y. Leblebici, and P. Ienne. Quantitative modelling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip. International Symposium on Low Power Electronics and Design.
9. R. Ho, K. Mai, and M. Horowitz. The future of wires. Proceedings of the IEEE,pages 490-504, April. 2001.
10. I.Saastamoinen, D.Siguenza-Tortosa, and J. Nurmi. Interconnect IP node for future system-on-chip designs. Proc. of The First IEEE International Workshop on Electronic Design, Test and Applications, pages 116-120, January. 2002.
11. J. Henkel et. al. On-chip networks: A scalable communication-centric embedded system design paradigm. Int. Conf. VLSI Design, 2004.
12. A. Jantsch and H. T. (Eds). Networks-on-chip. Kluwer., 2003.
13. N. Kavaldjiev, G. J. M. Smit, P. G. Jansen, and P. T. Wolkotte. A virtual channel Network-on-Chip for GT and BE traffic. Proc. of the International Symposium on VLSI (ISVLSI'06).
14. S. Murali and G. D. Micheli. Sunmap: A tool for automatic topology selection and generation for noes. Proc. of the Design, Automation conf.(DAC04), June. 2004.
15. L. Ni and P. McKinley. A survey of wormhole routing techniques in direct networks. IEEE Computer, pages 62-75, February. 1993.
16. U. Y. Ogras, J. Hu, and R. Marculescu. Key research problems in noc design: A holistic perspective. CODES+ISSS, September. 2005.