Bringing NoCs to 65 nm

IEEE Micro

Volumn 27, Issue 5, 2007, Pages 75-85

  Pullini, Antonio ^a   Angiolini, Federico ^b   Murali, Srinivasan ^b   Atienza, David ^c   De Micheli, Giovanni ^b   Benini, Luca ^b  

^a POLITECNICO DI TORINO   (Italy)

^b EPFL   (Switzerland)

^c UNIVERSIDAD COMPLUTENSE DE MADRID   (Spain)

Author keywords

Deep submicron design; Design aids; Design engineering; Interconnection networks; Low power electronics; Low power design; Management; Multicore architectures; Network on chip; On chip interconnection networks; Power management; Submicron design

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; INTERCONNECTION NETWORKS;

MULTICORE ARCHITECTURE; ON-CHIP INTERCONNECTION NETWORK; SUBMICRON DESIGN;

MICROPROCESSOR CHIPS;

EID: 36849004429     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2007.4378785     Document Type: Article

References (8)

1. L. Benini and G. De Micheli, "Networks on Chip: A New SoC Paradigm," Computer, vol. 35, no. 1, Jan. 2002, pp. 70-78.
2. W.J. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks," Proc. 38th Conf. Design Automation (DAC 01), ACM Press, 2001, pp. 684-689.
3. F. Angiolini et al., "Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness," Proc. Design, Automation and Test in Europe Conf. (DATE 06), IEEE Press, 2006, pp. 124-129.
4. A. Jantsch and H. Tenhunen, Eds., Networks on Chip, Kluwer Academic, 2003.
5. L. Benini and G.D. Micheli, Eds., Networks on Chips: Technology and Tools, Morgan Kaufmann, 2006.
6. A. Pullini et al., "Fault Tolerance Overhead in Network-on-Chip Flow Control Schemes," Proc. 18th Ann. Symp. Integrated Circuits and System Design (SBCCI 05), ACM Press, 2005, pp. 224-229.
7. S. Murali et al., "Designing Application-Specific Networks on Chips with Floorplan Information," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD 06), IEEE Press, 2006, pp. 355-362.
8. A. Pullini et al., "NoC Design and Implementation in 65 nm Technology," Proc. 1st Int'l Symp. Networks-on-Chip (NOCS 07), IEEE Press, 2007, pp. 273-282.