A layout-aware analysis of networks-on-chip and traditional interconnects for MPSoCs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 3, 2007, Pages 421-434

  Angiolini, Federico ^b   Meloni, Paolo ^a,c   Carta, Salvatore M ^c   Raffo, Luigi ^a,c   Benini, Luca ^a,b  

^a IEEE   (Italy)

^b UNIVERSITY OF BOLOGNA   (Italy)

^c UNIVERSITY OF CAGLIARI   (Italy)

Author keywords

Floorplan; Interconnection systems; Networks on chip (NoCs); Power consumption; Scalability; Synthesis flow

Indexed keywords

BANDWIDTH; COMPUTATIONAL COMPLEXITY; EMBEDDED SYSTEMS; OPTICAL INTERCONNECTS; PACKET NETWORKS; SCALABILITY;

FLOORPLAN; NETWORKS-ON-CHIP (NOCS); SYNTHESIS FLOW;

INTEGRATED CIRCUIT LAYOUT;

EID: 33847762802     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.888287     Document Type: Article

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