Fixed-outline floorplanning: Enabling hierarchical design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 11, Issue 6, 2003, Pages 1120-1135

  Adya, Saurabh N ^a   Markov, Igor L ^a  

^a University of Michigan   (United States)

Author keywords

Floorplanning; Hierarchical design; Physical design; Placement; VLSI CAD

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; MICROPROCESSOR CHIPS; PARETO PRINCIPLE; SIMULATED ANNEALING; VLSI CIRCUITS;

FIXED-OUTLINE FLOORPLANNING; HIERARCHICAL DESIGN; PHYSICAL DESIGN; PLACEMENT;

INTEGRATED CIRCUIT LAYOUT;

EID: 0742321357     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.817546     Document Type: Article

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