VHDL-based simulation environment for Proteo NoC

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn 2002-January, Issue , 2002, Pages 1-6

  Siguenza Tortosa D ^a   Nurmi, J ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

Communication channels; Computer architecture; Crosstalk; Design methodology; Integrated circuit interconnections; Intellectual property; Libraries; Network synthesis; Network on a chip; Software tools

Indexed keywords

COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER ARCHITECTURE; CROSSTALK; DESIGN; INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATED CIRCUIT TESTING; INTELLECTUAL PROPERTY; LIBRARIES; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; SYSTEMS ANALYSIS; VLSI CIRCUITS;

DESIGN METHODOLOGY; HIERARCHICAL TOPOLOGY; INTEGRATED CIRCUIT INTERCONNECTIONS; INTERCONNECTION STRUCTURE; NETWORK ON A CHIP; NETWORK SYNTHESIS; NETWORK-ON-CHIP ARCHITECTURES; SIMULATION ENVIRONMENT;

NETWORK-ON-CHIP;

EID: 84949187090     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2002.1224419     Document Type: Conference Paper

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