An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 2, Issue , 2004, Pages 878-883

  Rǎdulescu, Andrei ^a   Dielissen, John ^a   Goossens, Kees ^a   Rijpkema, Edwin ^a   Wielage, Paul ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; OPTIMIZATION; PACKET NETWORKS; PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS; QUEUEING NETWORKS; SUPERVISORY AND EXECUTIVE PROGRAMS; SYNCHRONIZATION; EXHIBITIONS;

BUS PROTOCOLS; NETWORK CONFIGURATION; ON-CHIP NETWORKS; SHARED-MEMORY ABSTRACTION;

INTERFACES (COMPUTER); ABSTRACTING;

BACKWARD COMPATIBILITY; BEST-EFFORT SERVICES; BUS PROTOCOL; FLEXIBLE NETWORKS; GUARANTEED SERVICE; MODULAR ARCHITECTURES; ON-CHIP NETWORKS; SHARED MEMORY;

EID: 3042660381     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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