A 51 mW 1.6GHz on-chip network for low-power heterogeneous SoC platform

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2003, Pages 112-113+476

  Lee, Kangmin ^a   Lee, Se Joong ^a   Kim, Sung Eun ^a   Choi, Hye Mi ^a   Kim, Donghyun ^a   Kim, Sunyoung ^a   Lee, Min Wuk ^a   Yoo, Hoi Jun ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS TRANSFER MODE; BANDWIDTH; CMOS INTEGRATED CIRCUITS; COMPUTER NETWORKS; ELECTRIC POWER UTILIZATION; FIELD PROGRAMMABLE GATE ARRAYS; PROGRAM PROCESSORS; QUALITY OF SERVICE; SIGNAL ENCODING; TOPOLOGY; TRANSCEIVERS;

CLOCK SYNCHRONIZATION; LOW ENERGY TRANSMISSION; ON CHIP NETWORK; SCALABILITY;

MICROPROCESSOR CHIPS;

EID: 2442689292     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)