Materials and processes for high k gate stacks: Results from the FEP transition center

ECS Transactions

Volumn 3, Issue 3, 2006, Pages 389-415

  Osburn, C M ^a   Campbell, S A ^b   Demkov, A ^c   Eisenbraun, E ^d   Garfunkel, E ^e   Gustafsson, T ^e   Kingon, A I ^a   Lee, J ^c   Lichtenwalner, D J ^a   Lucovsky, G ^f   Ma, T P ^g   Maria, J P ^a   Misra, V ^a   Nemanich, R J ^f   Parsons, G N ^f   Schlom, D G ^h   Stemmer, S ⁱ   Wallace, R M ^j   Whitten, J ^f  

^a North Carolina State University   (United States)

^b University of Minnesota   (United States)

^c UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^d STATE UNIVERSITY OF NEW YORK   (United States)

^e RUTGERS UNIVERSITY   (United States)

^f NORTH CAROLINA STATE UNIVERSITY   (United States)

^g Yale University   (United States)

^h PENNSYLVANIA STATE UNIVERSITY   (United States)

ⁱ Santa Barbara   (United States)

^j UNIVERSITY OF TEXAS AT DALLAS   (United States)

more..

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CRYSTAL DEFECTS; CRYSTALLIZATION; ELECTRODES; INTERFACES (MATERIALS); NANOTECHNOLOGY; PHASE TRANSITIONS;

EQUIVALENT OXIDE THICKNESSES; METAL GATE ELECTRODES; NANOCRYSTALLIZATION; TRAPPING LEVELS;

DIELECTRIC MATERIALS;

EID: 33847005971     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.2355729     Document Type: Conference Paper

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