A capacitance-based methodology for work function extraction of metals on high-κ

IEEE Electron Device Letters

Volumn 25, Issue 6, 2004, Pages 420-423

  Jha, Rashmi ^a   Gurganos, Jason ^a   Kim, Y H ^b   Choi, R ^b   Lee, Jack ^b   Misra, Veena ^a  

^a North Carolina State University   (United States)

^b The University of Texas at Austin   (United States)

Author keywords

Dual gate CMOS; Fermi level pinning; Gate electrodes; HfO2; High charges; Metal gates; Workfunction extraction

Indexed keywords

CALCULATIONS; DIELECTRIC MATERIALS; ELECTRIC POTENTIAL; ELECTRODES; ERRORS; GATES (TRANSISTOR); HAFNIUM COMPOUNDS; METALS; NUMERICAL ANALYSIS; RUTHENIUM ALLOYS; SILICA;

GATE DIELECTRIC STACKS; WORK FUNCTION EXTRACTION;

CMOS INTEGRATED CIRCUITS;

EID: 2942700372     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2004.829032     Document Type: Letter

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