Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 7, 2006, Pages 1350-1367

  Choi, Munkang ^a,b,c   Milor, Linda ^a,b  

^a IEEE   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^c GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Chemical mechanical polishing (CMP); Design for manufacturability; Lithography; Static timing analysis; Within die variation

Indexed keywords

DESIGN FOR MANUFACTURABILITY; STATIC TIMING ANALYSIS; WITHIN-DIE VARIATION;

CHEMICAL MECHANICAL POLISHING; COMPUTER AIDED SOFTWARE ENGINEERING; INTERFACES (COMPUTER); LITHOGRAPHY; NANOTECHNOLOGY; SEMICONDUCTOR DEVICE MANUFACTURE;

INTEGRATED CIRCUIT LAYOUT;

EID: 33744733086     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.855963     Document Type: Article

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