Static timing analysis based circuit-limited-yield estimation

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2002, Pages V/81-V/84

  Gattiker, Anne ^a   Nassif, Sani ^a   Dinakar, Rashmi ^b   Long, Chris ^b  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

^b IBA4 Microelectronics ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; MATHEMATICAL MODELS; PARAMETER ESTIMATION; PROBABILITY DISTRIBUTIONS; SENSITIVITY ANALYSIS;

CIRCUIT LIMITED YIELD ESTIMATION; DESIGN FOR QUALITY; STATIC TIMING ANALYSIS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036293045     PISSN: 02714310     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCAS.2002.1010645     Document Type: Article

References (10)

1. Timing yield estimation from static timing analysis
2. Delay variability: Sources, impacts and trends
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4. Realistic statistical worst-case simulations of VLSI circuits
5. Relating statistical mosfet model parameters variabilities to IC manufacturing process fluctuations enabling realistic worst case design
6. The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits
7. Timing verification and the timing analysis program
8. Fast power grid simulation