Analysis and justification of a simple, practical 2 1/2 -D capacitance extraction methodology

Proceedings - Design Automation Conference

Volumn , Issue , 1997, Pages 627-632

  Cong, Jason ^a   He, Lei ^a   Kahng, Andrew B ^a   Noice, David ^a   Shirali, Nagesh ^a   Yen, Steve H C ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; ELECTRIC CONDUCTORS; ELECTRIC WIRE; LOGIC GATES; PERMITTIVITY; VLSI CIRCUITS;

CADENCE SILICON ENSEMBLE; CAPACITANCE EXTRACTION METHODOLOGY;

INTEGRATED CIRCUIT LAYOUT;

EID: 0030686706     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/266021.266303     Document Type: Conference Paper

References (13)