Inductance model and analysis methodology for high-speed on-chip interconnect

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 10, Issue 6, 2002, Pages 730-745

  Gala, Kaushik ^a   Blaauw, David ^b   Zolotov, Vladimir ^a   Vaidya, Pravin M ^c,d   Joshi, Anil ^c  

^a MOTOROLA INC   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

^c CA and SI   (United States)

^d UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; COMPUTER SIMULATION; ELECTRIC RESISTANCE; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS;

INDUCTANCE MODELS;

INDUCTANCE;

EID: 0037002397     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2002.801619     Document Type: Article

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