An empirical three-dimensional crossover capacitance model for multilevel interconnect VLSI circuits

IEEE Transactions on Semiconductor Manufacturing

Volumn 13, Issue 2, 2000, Pages 219-227

  Wong, Shyh Chyi ^a   Lee, Trent Gwo Yann ^b   Ma, Dye Jyun ^c   Chao, Chuan Jane ^b  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^c NATIONAL CHUNG HSING UNIVERSITY   (Taiwan)

Author keywords

Closed form models; Crossover capacitance; Multilevel interconnects; VLSI circuits

Indexed keywords

APPROXIMATION THEORY; CAPACITANCE; ELECTRIC FIELDS; ELECTRIC WIRE; ELECTRODES; PERMITTIVITY; POISSON DISTRIBUTION; SUBSTRATES; VLSI CIRCUITS;

CLOSED FORM MODEL; MULTILEVEL METAL INTERCONNECTS; NUMERICAL FIELD SOLVER; ROOT MEAN SQUARE ERROR; THREE DIMENSIONAL CROSSOVER CAPACITANCE;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033699979     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.843637     Document Type: Article

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