Area fill synthesis for uniform layout density

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 10, 2002, Pages 1132-1147

  Chen, Yu ^a   Kahng, Andrew B ^b   Robins, Gabriel ^c   Zelikovsky, Alexander ^d  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c University of Virginia   (United States)

^d GEORGIA STATE UNIVERSITY   (United States)

Author keywords

Area fill; Chemical mechanical polishing; Hierarchical layout; Layout density control; Layout planarization; Monte Carlo methods

Indexed keywords

ALGORITHMS; CHEMICAL MECHANICAL POLISHING; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; LINEAR PROGRAMMING; MONTE CARLO METHODS;

AREA FILL; GREEDY ALGORITHMS; LAYOUT DENSITY CONTROL;

VLSI CIRCUITS;

EID: 0036811326     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.802278     Document Type: Article

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