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1
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84893767264
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Proposal for a new paradigm for design-manufacturing interface
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Sept
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W. Maly, "Proposal For A New Paradigm for Design-Manufacturing Interface", CMU Report, Sept. 1996.
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(1996)
CMU Report
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Maly, W.1
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2
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84893756531
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A new design-manufacturing paradigm
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W. Maly Ed., Research Report: CMUCAD-97-10
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W. Maly, H.T. Heineken, J. Khare and P.K. Nag, "A New Design-Manufacturing Paradigm," in Design for Manufacturability for the Next Decade, W. Maly Ed., Research Report: CMUCAD-97-10.
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Design for Manufacturability for the Next Decade
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Maly, W.1
Heineken, H.T.2
Khare, J.3
Nag, P.K.4
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4
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0020722214
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Yield estimation model for vlsi artwork evaluation
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Mar
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W. Maly and J. Deszczka, "Yield estimation model for VLSI artwork evaluation," Electron Lett., vol. 19, no. 6, pp. 226-227, Mar. 1983.
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(1983)
Electron Lett.
, vol.19
, Issue.6
, pp. 226-227
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Maly, W.1
Deszczka, J.2
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5
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0023561932
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Yield diagnosis through interpretation of tester data
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Washington D.C.
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W. Maly, B. Trifilo, R.A. Hughes, and A. Miller, "Yield Diagnosis Through Interpretation of Tester Data", In Proc. of ITC 87, Washington D.C., 1987, pp. 10-20.
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(1987)
Proc. of ITC 87
, pp. 10-20
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Maly, W.1
Trifilo, B.2
Hughes, R.A.3
Miller, A.4
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6
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0028737989
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Statistical analysis of particle/defect data experiments using Poisson and logistic regression
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Montreal, Que., Canada; 17-19, Oct
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J. G. Ramirez, R. S. Collica, and B.S. Cantell, "Statistical analysis of particle/defect data experiments using Poisson and logistic regression," IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 230-238, Montreal, Que., Canada; 17-19, Oct. 1994
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(1994)
IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
, pp. 230-238
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Ramirez, J.G.1
Collica, R.S.2
Cantell, B.S.3
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7
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0000777357
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Yield projections based on electrical fault distribution and circuit structure analysis
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I. Koren, Ed., New York, Plenum
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P. Schvan, D. Y. Montuno, and R. Hadaway, "Yield Projections Based on Electrical Fault Distribution and Circuit Structure Analysis", in Defect and Fault Tolerance in VLSI Systems, vol. 1, I. Koren, Ed., New York, Plenum, 1989, pp. 117-127.
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(1989)
Defect and Fault Tolerance in VLSI Systems
, vol.1
, pp. 117-127
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Schvan, P.1
Montuno, D.Y.2
Hadaway, R.3
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8
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84893778584
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G. Fortin, Private communication, 1986
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G. Fortin, Private communication, 1986.
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-
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9
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0011804351
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In-line yield prediction methodologies using patterned wafer inspection informational the 1996
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Oct
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R. K. Nurani, A. J. Strojwas, W. Maly, C. Ouyang, W. Shindo, R. Akella, M. McIntyre and J. Derret, "In-line yield prediction methodologies using patterned wafer inspection informational the 1996 Int. Symp. on Semiconductor Manufacturing, pp. 243-250, Oct. 1996.
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(1996)
Int. Symp. on Semiconductor Manufacturing
, pp. 243-250
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Nurani, R.K.1
Strojwas, A.J.2
Maly, W.3
Ouyang, C.4
Shindo, W.5
Akella, R.6
McIntyre, M.7
Derret, J.8
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10
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0029308749
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Quality and reliability impact of defect data analysis
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May
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E. Bruls, "Quality and Reliability Impact of Defect Data Analysis," IEEE Trans. on Semiconductor Manufacturing, no. 2, pp. 121-129, May 1995.
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(1995)
IEEE Trans. on Semiconductor Manufacturing
, Issue.2
, pp. 121-129
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Bruls, E.1
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11
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0024942778
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Qualification and quantification of process-induced product-related defects
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F. Camerick, P. A. G. Dirks, and J. A. G. Jess, "Qualification and Quantification of Process-Induced Product-Related Defects," in Proc. of Int. Test Conf., pp. 643-652, 1989.
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(1989)
Proc. of Int. Test Conf.
, pp. 643-652
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Camerick, F.1
Dirks, P.A.G.2
Jess, J.A.G.3
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12
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0028479701
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Extraction of defect size distributions in an IC layer using test structure data
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Aug
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J. B. Khare, W. Maly and M. E. Thomas, "Extraction of defect size distributions in an IC layer using test structure data," IEEE Trans. on Semiconductor Manufacturing, vol. 7, no. 3, pp. 354-368, Aug. 1994.
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(1994)
IEEE Trans. on Semiconductor Manufacturing
, vol.7
, Issue.3
, pp. 354-368
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Khare, J.B.1
Maly, W.2
Thomas, M.E.3
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13
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0027540685
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Defect level estimation of circuit testing using sequential statistical analysis
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Feb
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W.-B. Jone, "Defect Level Estimation of Circuit Testing Using Sequential Statistical Analysis," Trans. on Computer-Aided Design, Vol. 12, No. 2, pp. 336-348, Feb. 1993.
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(1993)
Trans. on Computer-Aided Design
, vol.12
, Issue.2
, pp. 336-348
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Jone, W.-B.1
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14
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0019530357
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Determining ic layout rules for cost minimization
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Feb
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R. D. Rung, "Determining IC Layout Rules for Cost Minimization," IEEE J. Solid-State Circuits, vol. SC-16, pp. 35-42, Feb. 1981.
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(1981)
IEEE J. Solid-State Circuits
, vol.SC-16
, pp. 35-42
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Rung, R.D.1
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15
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0022229576
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Statistical design rule developer
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Santa Clara, CA
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R. Razdan and A. J. Strojwas, "Statistical Design Rule Developer," in Proc. of ICCAD 85, Santa Clara, CA, 1985.
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(1985)
Proc. of ICCAD 85
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Razdan, R.1
Strojwas, A.J.2
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16
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0020846899
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Modeling of integrated circuit defect sensitivities
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Nov
-
C. H. Stapper, "Modeling of Integrated Circuit Defect Sensitivities," IBM Journal of Research and Development, Vol. 27, No. 6, pp. 549-557, Nov. 1983.
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(1983)
IBM Journal of Research and Development
, vol.27
, Issue.6
, pp. 549-557
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Stapper, C.H.1
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17
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27644592104
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Modeling of lithograph-related yield losses for cad of vlsi circuits
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July
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W. Maly, "Modeling of lithograph-related yield losses for CAD of VLSI circuits," IEEE Trans. on Computer-Aided Design, vol. 4, no. 4, pp. 166-177, July 1985.
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(1985)
IEEE Trans. on Computer-Aided Design
, vol.4
, Issue.4
, pp. 166-177
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Maly, W.1
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18
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0022102574
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Modeling the critical area in yield forecasts
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Aug. 85
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A. V. Ferris-Prabhu, "Modeling the Critical Area in Yield Forecasts," IEEE Journal of Solid-State Circuits, Vol. SC-20, No. 4, pp. 874-880, Aug. 85.
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IEEE Journal of Solid-State Circuits
, vol.SC-20
, Issue.4
, pp. 874-880
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Ferris-Prabhu, A.V.1
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19
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0001024129
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Yield model for manufacturing strategy planning and product shrink applications
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July
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W. Maly, H.T. Heineken and F. Agricola," Yield model for manufacturing strategy planning and product shrink applications," Semiconductor International, pp. 148-154, July 1994.
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(1994)
Semiconductor International
, pp. 148-154
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Maly, W.1
Heineken, H.T.2
Agricola, F.3
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20
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0029703533
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Yield loss forecasting in the early phases of the VLSI design process
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May
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H. T. Heineken, J. Khare, and W. Maly, "Yield loss forecasting in the early phases of the VLSI design process," Proc. CICC, pp. 27-30, May 1996.
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(1996)
Proc. CICC
, pp. 27-30
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Heineken, H.T.1
Khare, J.2
Maly, W.3
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23
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0030381239
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Detection of an antenna effect in VLSI designs
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W. Maly, C. H. Ouyang, S. Ghosh, and S. Maturi, "Detection of an antenna effect in VLSI designs," Proc. of 1996 Int. Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 86-94.
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(1996)
Proc. of Int. Symp. on Defect and Fault Tolerance in VLSI Systems
, pp. 86-94
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Maly, W.1
Ouyang, C.H.2
Ghosh, S.3
Maturi, S.4
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24
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0030717811
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CAD at the design manufacturability interface
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June 9-13
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H. T. Heineken, J. Khare and W. Maly, P. K. Nag, C. Ouyang, W. A. Pleskacz, "CAD at the Design Manufacturability Interface,"in Proc. of 1997 Design Automation Conference, June 9-13, 1997, pp. 321-326.
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(1997)
Proc. of 1997 Design Automation Conference
, pp. 321-326
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-
Heineken, H.T.1
Khare, J.2
Maly, W.3
Nag, P.K.4
Ouyang, C.5
Pleskacz, W.A.6
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25
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0031142594
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Simulation of yield/cost learning curves using Y4
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May
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P. K. Nag. W. Maly and H. Jacobs, "Simulation of yield/cost learning curves using Y4," IEEE Transactions on Semiconductor Manufacturing, May 1997,Vol. 10, No. 2, pp. 256-266.
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(1997)
IEEE Transactions on Semiconductor Manufacturing
, vol.10
, Issue.2
, pp. 256-266
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Nag. Maly, W.P.K.1
Jacobs, H.2
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26
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84893718841
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Design-Manufacturing interface: Part ii-applications
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Feb
-
W. Maly, H.T. Heineken, J. Khare, P.K. Nag, P. Simon and C. Ouyang, "Design-Manufacturing Interface: Part II-Applications," in Proceedings of DATE, Feb. 1998.
-
(1998)
Proceedings of DATE
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Maly, W.1
Heineken, H.T.2
Khare, J.3
Nag, P.K.4
Simon, P.5
Ouyang, C.6
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