Simulating the impact of pattern-dependent poly-CD variation on circuit performance

IEEE Transactions on Semiconductor Manufacturing

Volumn 11, Issue 4, 1998, Pages 552-556

  Stine, Brian E ^a,b   Boning, Duane S ^a,c   Chung, James E ^a,c   Ciplickas, Dennis J ^b   Kibarian, John K ^b  

^a USA   (United States)

^b PDF SOLUTIONS INC   (United States)

^c IEEE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; MATHEMATICAL MODELS; PERFORMANCE; RANDOM ACCESS STORAGE;

HOPKINS MODEL; POLYSILICON CRITICAL DIMENSION; STATIC RANDOM ACCESS MEMORY;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0032205065     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.728551     Document Type: Article

References (21)

1. P. Balaban and J. Golembeski, "Statistical analysis for practical circuit design," IEEE Trans. Circuits Syst. vol. CAS-22, pp. 100-108, Feb. 1975.
2. P. Rankin and R. Soin, "Efficient Monte Carlo yield prediction using control variates," in Proc. IEEE Int. Symp. Circuits Syst., Apr. 1981, vol. 1, pp. 143-148.
3. S. W. Director and G. Hatchel, "The simplicial approximation approach to design centering," IEEE Trans. Circuits Syst., vol. CAS-24, no. 7, pp. 363-372, July 1977.
4. J. Bandler and H. Abdel-Malek, "Optimal centering, tolerancing, and yield determination via updated approximations and cuts," IEEE Trans. Circuit Syst., vol. CAS-25, no. 10, pp. 853-871, Oct. 1978.
5. L. Vidigal and S. Director, "A design centering algorithm for nonconvex regions of acceptability," IEEE Trans. Computer-Aided Design, vol. CAD-1, pp. 13-24, Jan. 1982.
6. K. Tahim and R. Spence, "A radial exploration approach to manufacturing yield estimation and design centering," IEEE Trans. Circuits Syst., vol. CAS-26, pp. 78-774, Sept. 1979.
7. K. Singhal and J. Pinel, "Statistical design centering and tolerancing using parametric sampling," IEEE Trans. Circuits Syst., vol. CAS-28, no. 7, pp. 692-702, July 1981.
8. K. Antreich and R. Koblitz, "Design centering by yield prediction," IEEE Trans. Circuits Syst., vol. CAS-29, no. 2, pp. 88-95, Feb. 1982.
9. W. Maly and A. Strojwas, "Statistical simulation of the IC manufacturing process," IEEE Trans. Computer-Aided Design, vol. CAD-1, pp. 120-131, July 1982.
10. D. Hocevar, M. Lightner, and T. Trick, "An extrapolated yield approximation technique for use in yield maximization," IEEE Trans. Computer-Aided Design, vol. CAD-3, pp. 279-287, Oct. 1984.
11. M. Styblinski and L. Opalski, "Algorithms and software tools for IC yield optimization based on fundamental fabrication parameters," IEEE Trans. Computer-Aided Design, vol. CAD-5, pp. 79-89, Jan. 1986.
12. W. Maly, A. Strojwas, and S. Director, "VLSI yield prediction and estimation: A unified framework," IEEE Trans. Computer-Aided Design, vol. CAD-5, pp. 114-130, Jan. 1986.
13. M. Hatzilambrou, A. R. Neureuther, and C. J. Spanos, "Ring oscillator sensitivity to spatial process variation," in Proc. 1st Int. Workshop Statistical Metrology, June 1996.
14. B. Stine, D. Boning, J. Chung, D. Bell, and E. Equi, "Inter- and intra-die polysilicon critical dimension variation," in Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II, SPIE 1996 Symp. Microelectronic Manufacturing, Oct. 1996, Austin, TX.
15. D. Doherty Fitzgerald, "Analysis of polysilicon critical dimension variation for submicron CMOS processes," M.S. thesis, Dept. Elect. Eng. Comp. Sci., Mass. Inst. Technol., Cambridge, June 1994.
16. Y. Pati, A. Ghazanfarian, and R. Pease, "Exploiting structure in fast aerial image computation for integrated circuit patterns," IEEE Trans. Semiconduct. Manufact., vol. 10, pp. 62-73, Feb. 1997.
17. D. Cole, E. Barouch, U. Hollerbach, and S. Orszag, "Derivation and simulation of higher numerical aperture scalar aerial images," Jpn. J. Appl. Phys., vol. 31, p. 4110, 1992.
18. M. Bohr and Y. El-Mansy, "Technology for advanced high-performance microprocessors," IEEE Trans. Electron Devices, vol. 45, pp. 620-625, Mar. 1998.
19. Semiconductor Industry Association, The National Technology Roadmap for Semiconductors, San Jose, CA, 1994.
20. K. Rahmat, O. Nakagawa, S.-Y. Oh, J. Moll, and W. Lynch, "A scaling scheme for interconnect in deep-submicron processes," in IEDM Tech. Dig., Dec. 1995.
21. G. Thakar, V. McNeil, S. Madan, B. Riemenschneider, D. Rogers, J. McKee, R. Eklund, and R. Chapman, "A manufacturable high performance quarter micron CMOS technology using I-line lithography and gate linewidth reduction etch process," in Proc. 1996 Symp. VLSI Technology, June 1996, pp. 216-217.