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Volumn 10, Issue 6, 2002, Pages 799-805

Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion

Author keywords

Delay; Effective loop inductance; Inductance; Interconnect; Repeater insertion; Timing analysis

Indexed keywords

ELECTRIC LINES; SWITCHING; TELECOMMUNICATION REPEATERS;

EID: 0037002052     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2002.808426     Document Type: Article
Times cited : (26)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.