Elements of low power design for integrated systems

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2003-January, Issue , 2003, Pages 205-210

  Kang, S M S ^a  

^a University of California Santa Cruz   (United States)

Author keywords

Clocks; CMOS logic circuits; CMOS technology; Energy consumption; Integrated circuit technology; Logic design; Personal digital assistants; Power dissipation; Very large scale integration; Voltage

Indexed keywords

CLOCKS; CMOS INTEGRATED CIRCUITS; DESIGN; DIGITAL INTEGRATED CIRCUITS; ELECTRIC LOSSES; ELECTRIC POTENTIAL; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY DISSIPATION; ENERGY UTILIZATION; INTEGRATED CIRCUIT DESIGN; LOGIC CIRCUITS; LOGIC DESIGN; PERSONAL DIGITAL ASSISTANTS; POWER ELECTRONICS; THRESHOLD VOLTAGE; VLSI CIRCUITS;

CMOS LOGIC CIRCUITS; CMOS TECHNOLOGY; GATE OXIDE THICKNESS; INTEGRATED CIRCUIT TECHNOLOGY; INTEGRATED SYSTEMS; LOW POWER DESIGN TECHNIQUE; LOW-POWER DESIGN; SUB-100 NM TECHNOLOGIES;

LOW POWER ELECTRONICS;

EID: 1542299283     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2003.1231863     Document Type: Conference Paper

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