Precomputation-based sequential logic optimization for low power

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn , Issue , 1994, Pages 74-81

  Alidina, Mazhar ^a   Monteiro, Jose ^a   Devadas, Srinivas ^a   Ghosh, Abhijit ^a   Papaefthymiou, Marios ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK PARAMETERS; ELECTRIC NETWORK SYNTHESIS; LOGIC DESIGN; OPTIMIZATION;

PRECOMPUTATION BASED SEQUENTIAL LOGIC OPTIMIZATION; PRECOMPUTING;

SEQUENTIAL CIRCUITS;

EID: 0028710947     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (13)