A sub- 130-nm conditional keeper technique

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 5, 2002, Pages 633-638

  Alvandpour, Atila ^a,b   Krishnamurthy, Ram K ^a,b   Soumyanath, K ^a,b   Borkar, Shekhar Y ^a,b  

^a IEEE   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Burn in; Conditional; Dynamic circuits; Keeper; Leakage; Robustness

Indexed keywords

ACTIVE AREA REDUCTION; BURN IN CONDITIONAL KEEPER; CONDITIONAL KEEPER TECHNIQUE; WIDE DYNAMIC CIRCUITS;

COMPUTER SIMULATION; ELECTRIC CURRENT CONTROL; ELECTRIC NETWORK TOPOLOGY; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; MOSFET DEVICES; SPURIOUS SIGNAL NOISE;

VLSI CIRCUITS;

EID: 0036565318     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.997857     Document Type: Article

References (10)

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