A low-swing clock double-edge triggered flip-flop

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 5, 2002, Pages 648-652

  Kim, Chulwoo ^a,b   Kang, Sung Mo ^a,c  

^a IEEE   (United States)

^b IBM   (United States)

^c University of California Santa Cruz   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK DISTRIBUTION NETWORK; CLOCKED TRANSISTORS; CONDITONAL CAPTURE FLIP FLOP; DOUBLE EDGE TRIGGERED; INTERNAL NODE TRANSITION; REDUCED CLOCK SWING FLIP FLOP; SINGLE CLOCK FLIP FLOP; TRUE-SINGLE-PHASE-CLOCK; VERY DEEP SUBMICRON TECHNOLOGY;

COMPUTER SIMULATION; ENERGY UTILIZATION; LEAKAGE CURRENTS; LOGIC CIRCUITS; MOSFET DEVICES; PERFORMANCE; TRIGGER CIRCUITS;

FLIP FLOP CIRCUITS;

EID: 0036564730     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.997859     Document Type: Article

References (10)

1. A new single clock flip-flop for half-swing clocking
2. A reduced clock-swing flip-flop (RCSFF) for 63% clock power reduction
3. Half-swing clocking scheme for 75% power saving in clocking circuitry
4. Flow-through latch and edge-triggered flip-flop hybrid elements
5. Semi-dynamic and dynamic flip-flops with embedded logic
6. Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
7. Conditional-capture flip-flop technique for statistical power reduction
8. Flip-flop selection technique for power-delay trade-off
9. A low-swing clock double edge-triggered flip-flop