1-V high-speed MTCMOS circuit scheme for power-down applications

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1995, Pages 125-126

  Shigematsu, Satoshi ^a   Mutoh, Shin'ichiro ^a   Matsuya, Yasuyuki ^a   Yamada, Junzo ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CRITICAL PATH ANALYSIS; ELECTRIC NETWORK ANALYSIS; ELECTRIC POWER SUPPLIES TO APPARATUS; FLIP FLOP CIRCUITS; LEAKAGE CURRENTS; LSI CIRCUITS; PERFORMANCE; POWER SUPPLY CIRCUITS; SHIFT REGISTERS;

BALLOON CIRCUIT; HOLDING CIRCUIT; MULTI THRESHOLD CMOS CIRCUITS; POWER DOWN APPLICATIONS; SCAN REGISTER;

CMOS INTEGRATED CIRCUITS;

EID: 0029542965     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)