Gate-over-driving CMOS architecture for 0.5 V single-power-supply-operated devices

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 40, Issue , 1997, Pages 290-291

  Iwata, Toru ^a   Yamauchi, Hiroyuki ^a   Akamatsu, Hironori ^a   Terada, Yutaka ^a   Matsuzawa, Akira ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITOR STORAGE; ELECTRIC LOADS; ELECTRIC POWER SUPPLIES TO APPARATUS; FREQUENCY RESPONSE; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; LOGIC CIRCUITS; LOGIC GATES; MICROPROCESSOR CHIPS; THRESHOLD ELEMENTS; VOLTAGE CONTROL;

SINGLE POWER SUPPLY OPERATED DEVICES;

CMOS INTEGRATED CIRCUITS;

EID: 0031069346     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)