An optimal design of leak-proof SRAM cell using MCDM method

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5117, Issue , 2003, Pages 478-484

  Wang, Qi ^a   Kang, Sung Mo ^a  

^a University of California Santa Cruz   (United States)

Author keywords

MCDM strategy; Optimum design; SRAM

Indexed keywords

CACHE MEMORY; LEAKAGE CURRENTS; OPTIMIZATION; RANDOM ACCESS STORAGE;

ON CHIP CACHE; POWER DISSIPATION;

CMOS INTEGRATED CIRCUITS;

EID: 0042329134     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.499068     Document Type: Conference Paper

References (8)

1. S. Borkar. Design Challenges of Technology Scaling. IEEE Micro, 19(4):23-29, July 1999.
2. V. De S. Borkar. Technology and Design Challenges for Low Power and High Performance. Proc. of the International Symposium on Low Power Electronics and Design, pages 163-168, August 1999.
3. C. Wann. A Comparative Study of Advanced MOSFET Concepts. Proc. of the International Electron Devices Meeting, pages 1742-1753, October 1996.
4. H. Eschenauer J. Koski, A. Osyczka. Multicriteria Design Optimization Procedures and Applications. 1990
5. T SRAM Cells with Full-Swing Single-ended Bit line Sensing for High-performance On-chip cache in 0.13μm Technology Generation. Proc. of the International Symposium on Low Power Electronics and Design, 2000.
6. T SRAM Cells with Full-Swing Single-ended Bit line Sensing for High-performance On-chip cache. IEEE Trans. on Very Large Scale Integration Systems, pages 91-95, April 2002.
7. N. Azizi, A. Moshovos, F. N. Najm. Low-Leakage Asymmetric-cell SRAM. Proc. of the International Symposium on Low Power Electronics and Design, August 2002.
8. G. Balamurugan N. R. Shanbhag. A Noise-Tolerant Dynamic Circuit Design Technique. Custom Integrated Circuits Conference, May 2000.