Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 10, Issue 2, 2002, Pages 91-95

  Hamzaoglu, Fatih ^a   Ye, Yibin ^b   Keshavarzi, Ali ^b   Zhang, Kevin ^b   Narendra, Siva ^b   Borkar, Shekhar ^b   Stan, Mircea ^a   De, Vivek ^b  

^a University of Virginia   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Dual VT; Noise recovery; Read stability; Single ended sensing; SRAM

Indexed keywords

BUFFER STORAGE; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; THRESHOLD VOLTAGE;

ON-CHIP CACHE; SINGLE-ENDED BIT LINE SENSING;

STATIC RANDOM ACCESS STORAGE;

EID: 0036542680     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.994983     Document Type: Article

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