Reliability improvement of Cu interconnects by additional anneal between Cu CMP and barrier CMP

Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003

Volumn , Issue , 2003, Pages 92-94

  Harada, T ^a   Kobayashi, K ^b   Takahashi, M ^b   Nii, K ^a   Ikeda, A ^a   Ueda, T ^a   Yabu, T ^a  

^a PANASONIC CORPORATION   (Japan)

^b Engineering Department Matsushita Semi Conductor Engineering Co Ltd   (Japan)

Author keywords

Degradation; Electrical resistance measurement; Electromigration; Integrated circuit interconnections; Minimization; Reliability engineering; Simulated annealing; Temperature; Tensile stress; Testing

Indexed keywords

COPPER; DEGRADATION; ELECTROMIGRATION; INTEGRATED CIRCUIT TESTING; INTERFACES (MATERIALS); OPTIMIZATION; RELIABILITY; SILICON NITRIDE; SIMULATED ANNEALING; TEMPERATURE; TENSILE STRESS; TENSILE TESTING; TESTING;

CU-INTERCONNECTS; DEVICE PERFORMANCE; ELECTRICAL RESISTANCE MEASUREMENT; INTEGRATED CIRCUIT INTERCONNECTIONS; RELIABILITY ENGINEERING; RELIABILITY IMPROVEMENT; STRESS-INDUCED VOIDING; SURFACE SMOOTHING;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84944029514     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2003.1219722     Document Type: Conference Paper

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