An optimized integration scheme for 0.13 μm technology node dual-damascene Cu interconnect

Proceedings of the IEEE 2000 International Interconnect Technology Conference, IITC 2000

Volumn , Issue , 2000, Pages 273-275

  Lin, Shyue Shyh ^a   Chen, Chih Wei ^a   Huang, Shien Ming ^a   Kang, Tsung Kuei ^a   Yeh, Chen Nan ^a   Li, Tsyr Lih ^a   Tsui, Bing Yue ^b   Hsia, C C ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATION;

DUAL DAMASCENE; ELECTRICAL SIMULATION; GLOBAL INTERCONNECTS; INTEGRATION SCHEME; NITRIDE LAYERS; PROCESS WINDOW; SACRIFICIAL LAYER; TECHNOLOGY NODES;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84962896280     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2000.854346     Document Type: Conference Paper

References (2)

1. J. Torres, 1999 IITC Conference, p.c253.
2. R. Iggulden et al., 1998 VMIC Conference, p.19.