-
1
-
-
0029520956
-
Phase edge lithography for sub-0.1μm electrical channel length in a 200mm full CMOS process
-
Kyoto, June 6-8, IEEE Press, Piscataway, N.J.
-
Agnello, P., Newman, T., Crabbe, E., Subbanna, S., Ganin, E., Liebmann, L., Comfort, J., and Sunderland, D. Phase edge lithography for sub-0.1μm electrical channel length in a 200mm full CMOS process. In Tech. Dig. of the Symposium on VLSI Technology (Kyoto, June 6-8, 1995), IEEE Press, Piscataway, N.J., pp. 79-80.
-
(1995)
Tech. Dig. of the Symposium on VLSI Technology
, pp. 79-80
-
-
Agnello, P.1
Newman, T.2
Crabbe, E.3
Subbanna, S.4
Ganin, E.5
Liebmann, L.6
Comfort, J.7
Sunderland, D.8
-
2
-
-
0031121270
-
Technology challenges for integration near and below 0.1μm
-
April
-
Asai, S., and Wada, Y. Technology challenges for integration near and below 0.1μm. Proc. IEEE 85, 4 (April 1997), 505-520.
-
(1997)
Proc. IEEE
, vol.85
, Issue.4
, pp. 505-520
-
-
Asai, S.1
Wada, Y.2
-
3
-
-
0029547914
-
Interconnect scaling - The real limiter to high-performance ULSI
-
Washington, D.C., Dec. 10-13, IEEE Press, Piscataway, N.J.
-
Bohr, M. Interconnect scaling - The real limiter to high-performance ULSI. In Tech. Dig. of the International Electron Devices Meeting (Washington, D.C., Dec. 10-13, 1995), IEEE Press, Piscataway, N.J., pp. 241-244.
-
(1995)
Tech. Dig. of the International Electron Devices Meeting
, pp. 241-244
-
-
Bohr, M.1
-
4
-
-
0028754969
-
A high-performance 0.35μm logic technology for 3.3V and 2.5V operation
-
San Francisco, Dec. 11-14, IEEE Press, Piscataway, N.J.
-
Bohr, M., Ahmed, S., Brigham, L., Chau, R., Gasser, R., Green, R., Hargrove, W., Lee, E., Natter, R., Thompson, S., Weldon, K., and Yang, S. A high-performance 0.35μm logic technology for 3.3V and 2.5V operation. In Tech. Dig. of the International Electron Devices Meeting (San Francisco, Dec. 11-14, 1994), IEEE Press, Piscataway, N.J., pp. 273-276.
-
(1994)
Tech. Dig. of the International Electron Devices Meeting
, pp. 273-276
-
-
Bohr, M.1
Ahmed, S.2
Brigham, L.3
Chau, R.4
Gasser, R.5
Green, R.6
Hargrove, W.7
Lee, E.8
Natter, R.9
Thompson, S.10
Weldon, K.11
Yang, S.12
-
5
-
-
0030383519
-
A high-performance 0.25μm logic technology optimized for 1.8V operation
-
San Francisco, Dec. 8-11, IEEE Press, Piscataway, N.J.
-
Bohr, M., Ahmed, S., Ahmed, S., Bost, M., Ghani, T., Greason, J., Hainsey, R., Jan, C., Packan, P., Sivakumar, S., Thompson, S., Tsai, J., and Yang, S. A high-performance 0.25μm logic technology optimized for 1.8V operation. In Tech. Dig. of the International Electron Devices Meeting (San Francisco, Dec. 8-11, 1996), IEEE Press, Piscataway, N.J., pp. 847-850.
-
(1996)
Tech. Dig. of the International Electron Devices Meeting
, pp. 847-850
-
-
Bohr, M.1
Ahmed, S.2
Ahmed, S.3
Bost, M.4
Ghani, T.5
Greason, J.6
Hainsey, R.7
Jan, C.8
Packan, P.9
Sivakumar, S.10
Thompson, S.11
Tsai, J.12
Yang, S.13
-
6
-
-
0016116644
-
Design of ion-implanted MOSFETs with very small physical dimensions
-
Oct.
-
Dennard, R., Gaensslen, F., Yu, H., Rideout, V., Bassous, E., and LeBlanc, A. Design of ion-implanted MOSFETs with very small physical dimensions. IEEE J. Solid State Circuits SC-9, 5 (Oct. 1974), 256-268.
-
(1974)
IEEE J. Solid State Circuits
, vol.SC-9
, Issue.5
, pp. 256-268
-
-
Dennard, R.1
Gaensslen, F.2
Yu, H.3
Rideout, V.4
Bassous, E.5
LeBlanc, A.6
-
7
-
-
0031122158
-
CMOS scaling into the nanometer range
-
April
-
Taur, Y., Buchanan, D., Chen, W., Frank, D., Ismail, K., Lo, S., Sai-Halasz, G., Viswanathan, R., Wann, H., Wind, S., and Wong, H,. CMOS scaling into the nanometer range. Proc. IEEE 85, 4 (April 1997), 486-504.
-
(1997)
Proc. IEEE
, vol.85
, Issue.4
, pp. 486-504
-
-
Taur, Y.1
Buchanan, D.2
Chen, W.3
Frank, D.4
Ismail, K.5
Lo, S.6
Sai-Halasz, G.7
Viswanathan, R.8
Wann H9
Wind, S.10
Wong, H.11
|