Design rule methodology to improve the manufacturability of the copper CMP process

Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002

Volumn , Issue , 2002, Pages 99-101

  Lakshminarayanan, S ^a   Wright, P ^a   Pallinti, J ^b  

^a AGERE SYSTEMS   (United States)

^b LSI Logic   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL MECHANICAL POLISHING; SHEET RESISTANCE;

DESIGN RULES; FEATURE INTERACTIONS; MANUFACTURABILITY; METAL LAYER; MULTI LEVEL INTERCONNECTS; PATTERN DENSITY EFFECTS; SHEET RESISTANCE VARIATION; SPACE BETWEEN;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84961696210     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2002.1014900     Document Type: Conference Paper

References (4)

1. Vikas Mehrotra and Duane Boning, "Technology scaling impact of variation on clock skew and interconnect delay", in IITC 2001, pp. 122-124.
2. Venkat Kolagunta et. al, "Inline monitoring of multi-level dual inlaid copper interconnect technologies", in IITC 2000, pp. 247-249.
3. T. Park et. al, "Pattern and process dependencies in copper Damascene chemical mechanical polishing processes", in VMIC 1998.
4. Q-T. Jiang, M-H. Tsai and R.H. Havemann, "Line width dependence of copper resistivity", in IITC 2001, pp. 227-229.