Influence of process chamber ambient on SiOC (k = 2.9) ILD Cu damascene ashing

IEEE Transactions on Semiconductor Manufacturing

Volumn 17, Issue 3, 2004, Pages 305-310

  Tokashiki, Ken ^a   Maruyama, Takuya ^a   Nishizawa, Atsushi ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

All in One process; Ashing; Chamber ambient; Cu damascene; Low k

Indexed keywords

ADHESION; CHEMICAL VAPOR DEPOSITION; DEGRADATION; DIELECTRIC MATERIALS; ETCHING; OXYGEN; PHOTORESISTS;

ASHING; CHAMBER AMBIENT; CU DAMASCENE; ION-ASSIST ASHING;

SILICON;

EID: 4344687584     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2004.831927     Document Type: Conference Paper

References (6)

1. H. Nambu, A. Nishizawa, E. Soda, and K. Tokashiki, "Study of ashing technology for 90 nm and below low-k/Cu damascene interconnect," in Proc. Dry Process Int. Symp., 2002, pp. 15-20.
2. L.-H. Chen, S. Hoshino, T. Hayakawa, K. Maekawa, and K. Inazawa, "Dual damascene scheme and etch/ash damage of porous MSQ," in Proc. Dry Process Int. Symp., 2002, pp. 27-31.
3. K. Yonekawa, S. Sakamori, K. Goto, M. Matsuura, N. Fujiwara, and M. Yoneda, "Investigation of ashing damage to ulta-low-k dielectric material," in Proc. Dry Process Int. Symp., 2002, pp. 21-26.
4. K. Yonekawa, K. Goto, M. Matsuura, N. Fujiwara, and K. Tsujimoto, "Low damage damascene formation using inorganic porous low-k material," in Proc. Dry Process Int. Symp., 2003, pp. 19-24.
5. M. Yamanaka, H. Yuasa, T. Otsuka, and S. Sakamori, "Low damage ashing for CVD-SiOC film by using H2O plasma," in Proc. Dry Process Int. Symp., 2003, pp. 145-149.
6. E. A. Hudson, R. Ammapragada, D. Keil, J. Zhou, and K. Takeshita, "Memory effect for multi-step in situ plasma processing," in Proc. Dry Process Int. Symp., 2003, pp. 25-30.