Highly reliable Cu/low-k dual-damascene interconnect technology with hybrid (PAE/SiOC) dielectrics for 65 nm-node high performance eDRAM

Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003

Volumn , Issue , 2003, Pages 9-11

  Kajita, A ^a   Usui, T ^a   Yamada, M ^a   Ogawa, E ^a   Katata, T ^a   Sakata, A ^a   Miyajima, H ^a   Kojima, A ^a   Kanamura, R ^b   Ohoka, Y ^b   Kawashima, H ^b   Tabuchi, K ^b   Nagahata, K ^b   Kato, Y ^b   Hayashi, T ^b   Kadomura, S ^b   Shibata, H ^a  

^a TOSHIBA CORPORATION   (Japan)

^b SONY CORPORATION   (Japan)

Author keywords

Atherosclerosis; Dielectrics; Electric resistance; Etching; Filling; Propulsion; Robustness; Shape; Sputtering; Transmission electron microscopy

Indexed keywords

DIELECTRIC MATERIALS; ELECTRIC RESISTANCE; ETCHING; FILLING; HIGH RESOLUTION TRANSMISSION ELECTRON MICROSCOPY; NANOTECHNOLOGY; PROPULSION; ROBUSTNESS (CONTROL SYSTEMS); SPUTTERING; TRANSMISSION ELECTRON MICROSCOPY;

ATHEROSCLEROSIS; DUAL DAMASCENE INTERCONNECT; MEAN TIME TO FAILURE; PVD-BARRIER METAL; SHAPE; STACKED MASK PROCESS; STRESS-INDUCED VOIDING; THERMAL CYCLE TESTS;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 14844296709     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2003.1219697     Document Type: Conference Paper

References (4)

1. N. Okada et al., Proc. of IITC (2002) p.136.
2. J. Abe al., Proceedings of Int. Symp. on Dry Process (2001) p.187.
3. K. Higashi et al., Proc. of IITC (2002) p.15.
4. M. Hussein et al., Proc. of IITC (2002) p.18.