A manufacturable copper/low-k SiOC/SiCN process technology for 90 nm-node high performance eDRAM

Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002

Volumn , Issue , 2002, Pages 15-17

  Higashi, K ^a   Nakamura, N ^a   Miyajima, H ^a   Satoh, S ^b   Kojima, A ^a   Abe, J ^a   Nagahata, K ^c   Tatsumi, T ^c   Tabuchi, K ^c   Hasegawa, T ^c   Kawashima, H ^c   Arakawa, S ^a   Matsunaga, N ^a   Shibata, H ^a  

^a TOSHIBA CORPORATION   (Japan)

^b Manufacturing Engineering Department   (Japan)

^c SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

LOW-K DIELECTRIC; NANOTECHNOLOGY;

ASHING PROCESS; DUAL DAMASCENE PROCESS; DUAL DAMASCENE STRUCTURES; EMBEDDED DRAM; PROBLEMS AND SOLUTIONS; PROCESS TECHNOLOGIES; SICN LAYERS; STACKED MASK PROCESS;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84961683038     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2002.1014873     Document Type: Conference Paper

References (6)

1. J. Abe, et al., Dry Process Symposium, 187(2001)
2. K. Higashi, et al., The Japan Society of Applied Physics spring symposium (Japanese), 29P-YA-11(2000)
3. Y. Shimooka, et al., The Institute of Electronics. Information and Communication Engineers, Technical report of IEICE (Japanese), SDM2001-180
4. Simon Lin, et al., IITC. 146(2001)
5. S. A. Lytle, et al., IEDM Tech. (2001)
6. N. Iwasaki, et al., Advanced Metallization Conference 2001: Asian Session, P42-43