Design Optimization of One-Turn Helix: A Novel Compliant Off-Chip Interconnect

IEEE Transactions on Advanced Packaging

Volumn 26, Issue 2, 2003, Pages 106-112

  Zhu, Qi ^a   Ma, Lunyu ^a   Sitaraman, Suresh K ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Compliance; Design optimization; Interconnect; Off chip; Response surface; Wafer level

Indexed keywords

ELECTRONICS PACKAGING; MICROPROCESSOR CHIPS; OPTIMIZATION; SILICON WAFERS; THERMAL EXPANSION;

WAFER-LEVEL PACKAGING;

INTEGRATED CIRCUITS;

EID: 0141882977     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2003.817343     Document Type: Article

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