Stress-induced voiding phenomena for an actual CMOS LSI interconnects

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2002, Pages 753-756

  Yoshida, K ^a   Fujimaki, T ^a   Miyamoto, K ^a   Honma, T ^a   Kaneko, H ^a   Nakazawa, H ^a   Morita, M ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CMOS INTEGRATED CIRCUITS; COPPER; DIFFUSION; FABRICATION; MICROPROCESSOR CHIPS; TENSILE STRESS; TRANSMISSION ELECTRON MICROSCOPY;

STRESS INDUCED VOIDING (SIV);

LSI CIRCUITS;

EID: 0036932387     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. E. T. Ogawa, et al. "Stress-Induced Voiding Under Vias Connected Wide Cu Metal Leads" IRPS (2002)
2. G.B.Alers, et al., "Trade-off between reliability and post-CMP defects during recrystallization anneal for copper damascene interconnects" IRPS (2001)
3. Qing-Tang Jiang, et al., "Optimization of Annealing Conditions for Dual Damascene Cu Microstructures and Via Chain Yield" VLSI Tech. (2001)
4. Byung-Lyul Park, et al., "Mechanism of Stress-Induces Voids in Multi-Level Cu Interconnects" IITC (2002)