Opposite-channel-based injection of hot-carriers in SOI MOSFET's: Physics and applications

IEEE Transactions on Electron Devices

Volumn 45, Issue 5, 1998, Pages 1147-1154

  Loannou, Dimitris E ^a   Duan, Franklin L ^a   Sinha, Shankar P ^b   Zaleski, Andrej ^a,c  

^a Krasnow Institute for Advanced Study   (United States)

^b HONEYWELL TECHNOLOGY CENTER   (United States)

^c USA   (United States)

Author keywords

EPROM; Hot carriers; Interface phenomena; Silicon on insulator technology; SIMOX

Indexed keywords

COMPUTER SIMULATION; HOT CARRIERS; INTERFACES (MATERIALS); ION IMPLANTATION; PROM; SILICON ON INSULATOR TECHNOLOGY;

FULLY DEPLETED (FD) DEVICES; OPPOSITE CHANNEL BASED INJECTION (OCBI); PARTIALLY DEPLETED (PD) DEVICES;

MOSFET DEVICES;

EID: 0032070815     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.669576     Document Type: Article

References (38)

1. J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI. Norwell, MA: Kluwer, 1991.
2. S. Cristoloveanu and S. S. Li, Electrical Characterization of Silicon-onInsulator Materials and Devices. Norwell, MA: Kluwer, 1995.
3. H. K. Lim and J. G. Possum, "Threshold voltage of thin-film silicon-oninsulator (SOI) MOSFET's," IEEE Trans. Electron Devices, vol. ED-30, pp. 1244-1251, Oct. 1983.
4. B. Mazhari and D. E. loannou, "Surface potential at threshold in thinfilm SOI MOSFET's," IEEE Trans. Electron Devices, vol. 40, pp. 1129-1133, June 1993.
5. D. J. Wouters, J.-P. Colinge, and H. E. Maes, "Subthreshold slope in thin-film SOI MOSFET's," IEEE Trans. Electron Devices, vol. 37, pp. 1022-1033, Apr. 1990.
6. B. Mazhari, S. Cristoloveanu, D. E. loannou, and A. L. Caviglia, "Properties of ultra-thin wafer-bonded silicon-on-insulator MOSFET's," IEEE Trans. Electron Devices, vol. 38. pp. 1289-1295, June 1991.
7. H. K. Lim and J. G. Possum, "Current-voltage characteristics of thinfilm SOI MOSFET's in strong inversion," IEEE Trans. Electron Devices, vol. ED-31, pp. 401-108, Apr. 1984.
8. K. K. Young, "Short-channel effect in fully-depleted SOI MOSFET's," IEEE Trans. Electron Devices, vol. 36, pp. 339-102, Feb. 1989.
9. "Avalanche-induced drain-source breakdown in silicon-oninsulator n-MOSFET's," IEEE Trans. Electron Devices, vol. 35, pp. 426-131, Apr. 1988.
10. J. Y. Choi and J. G. Possum, "Analysis and control of floating-body bipolar effects in fully-depleted submicrometer SOI MOSFET's," IEEE Trans. Electron Devices, vol. 38, pp. 1384-1391, June 1991.
11. J. Tihanyi and H. Schlotterer, "Influence of floating substrate potential on the characteristics of ESFI MOS transistors," Solid State Electron., vol. 18, pp. 309-313, Mar. 1975.
12. S. S. Eaton and B. Lalevic, " Effect of floating substrate on the operation of silicon-on-sapphire transistors," IEEE Trans. Electron Devices, vol. ED-25, pp. 907-912, Aug. 1978.
13. D. Suh and J. G. Fossum, "Dynamic floating-body instabilities in partially-depleted SOI CMOS circuits," in 1EDM Tech. Dig., 1994, pp. 661-664.
14. A. Wei and D. A. Antoniadis, "Measurement of transient effects in SOI DRAM/SRAM access transistors," IEEE Electron Device Lett., vol. 17, pp. 193-196, May 1996.
15. P. K. McLarty, D. E. loannou, and J.-P. Collinge, "Bulk traps in ultrathin SIMOX MOSFET's by current DLTS," IEEE Electron Device Lett., vol. EDL-9, pp. 545-547, Oct. 1986.
16. D. E. loannou, S. Cristoloveanu, M. Mukherjee, and B. Mazhari, "Characterization of carrier generation in enhancement-mode SOI MOSFET's," IEEE Electron Device Lett., vol. 11, pp. 409-411, Sept. 1990.
17. S. P. Sinha, A. Zaleski, and D. E. loannou, "Investigation of carrier lifetime in fully-depleted enhancement and accumulation mode MOSFET's," IEEE Trans. Electron Devices, vol. 41, pp. 2413-2416, Dec. 1994.
18. D. E. loannou, X. Zhong, B. Mazhari, G. J. Campisi, and H. L. Hughes, "Interface characterization of fully-depleted SOI MOSFET's by the dynamic transconductance technique," IEEE Electron Device Lett., vol. 12, pp. 430-432, Aug. 1991.
19. D. E. loannou, "Current status of hot-carrier effects in SOI MOSFET's," in Proc. IEEE Int. SOI Conf., 1994, pp. 1-2.
20. S. Cristoloveanu, S. M. Gulwadi, D. E. loannou, G. J. Campisi, and H. L. Hughes, "Hot-electron-induced degradation of front and back channels in partially- and fully-depleted SIMOX MOSFET's," IEEE Electron Device Lett., vol. 13, pp. 603-605, Dec. 1992.
21. A. Zaleski, D. E. loannou, G. J. Campisi, and H. L. Hughes, "Successive charging/discharging of gate oxides in SOI MOSFET's by sequential hot-electron stressing of front/back channel," IEEE Electron Device Lett., vol. 14, pp. 435-437, Sept. 1993.
22. A. Zaleski, S. P. Shankar, D. E. loannou, G. J. Campisi, and H. L. Hughes, "Opposite-channel-based charge injection in SOI MOSFET's under hot-carrier stress," IEEE Trans. Electron Devices, vol. 42, pp. 1697-1700, Sept. 1995.
23. N. S. Saks, P. L. Heremans, L. Van Den Hove, H. E. Maes, R. F. De Keersmaecker, and G. J. Declerc, "Observation of hot-hole injection in NMOS transistors using a modified floating-gate technique," IEEE Trans. Electron Devices, vol. ED-33, pp. 1529-1533, Oct. 1986.
24. K. R. Hofman, C. Werner, W. Weber, and G. Dorda, "Hot-electron and hole-emission effects in short n-channel MOSFET's," IEEE Trans. Electron Devices, vol. ED-32, pp. 691-699, Mar. 1985.
25. SILVACO International, Santa Clara, CA 95054.
26. S. Tarn, P.-K. Ko, and C. Hu, "Lucky-electron model of channel hotelectron injection in SOI MOSFET's," IEEE Trans. Electron Devices, vol. ED-31, pp. 1116-1125, Sept. 1984.
27. F. L. Duan, S. P. Shankar, D. E. loannou, and F. T. Brady, "LDD design tradeoffs for single transistor latch-up and hot-carrier degradation control in accumulation mode FD SOI MOSFET's," IEEE Trans. Electron Devices, vol. 44, pp. 972-977, June 1997.
28. G. A. Armstrong, J. R. Davis, and A. Doyle, "Characterization of bipolar snapback and breakdown voltage in thin-film SOI transistors by twodimensional simulation," IEEE Trans. Electron Devices, vol. 38, pp. 328-336, Feb. 1991.
29. L. T. Su, H. Fang, J. E. Chung, and D. A. Antoniadis, "Hot-carrier effects in fully-depleted SOI NMOSFET's," in IEDM Tech. Dig., 1992, pp. 349-352.
30. A. Zaleski, "Opposite-channel-based-hot-carrier injection in SOI MOSFET's," Ph.D. dissertation, George Mason Univ., Fairfax, VA, Nov. 1996.
31. S. P. Sinha, "Hot-carrier reliability of SOI MOSFET's and applications to nonvolatile memories," Ph.D. dissertation, George Mason Univ., Fairfax, VA, Feb. 1997.
32. G. A. Armstrong, "Simulation of ultra thin film SOI transistors using a nonlocal ballistic model for impact ionization," Solid-State Electron., vol. 35, pp. 1761-1770, Dec. 1992.
33. N. Kistler and J. Woo, "Detailed characterization and analysis of breakdown voltage in fully depleted SOI n-MOSFET's," IEEE Trans. Electron Devices, vol. 41, pp. 1217-1221, July 1994.
34. S. P. Sinha, F. L. Duan, D. E. loannou, W. C. Jenkins, and H. L. Hughes, "Time dependence power laws of hot-carrier degradation in SOI MOSFET's," in Proc. 1996 IEEE Int. SOI Conf., pp. 18-19.
35. S. P. Sinha, A. Zaleski, D. E. loannou, G. J. Campisi, and H. L. Hughes, "Hot hole induced interface state generation and annihilation in SOI MOSFET's," IEEE Electron Device Lett., vol. 17, pp. 121-123, Mar. 1996.
36. A. Zaleski, D. E. loannou, D. Flandre, and J.-P. Colinge, "Design and performance of a new flash memory EEPROM on SOI(SIMOX) substrates," in Proc. IEEE Int. SOI Conf., Oct. 1994, pp. 13-14.
37. B. S. Doyle, K. R. Mistry, and J. Faricelli, "Examination of the time power law dependencies in hot-carrier stressing on n-MOS transistors," IEEE Electron Device Lett., vol. 18, pp. 51-53, Feb. 1997.
38. C. T. Wang, Ed., Hot Carrier Design Considerations for MOS Devices and Circuits. New York: Van Nostrand, 1992.