Subthreshold Slope in Thin-Film SOI MOSFET’s

IEEE Transactions on Electron Devices

Volumn 37, Issue 9, 1990, Pages 2022-2033

  Wouters, Dirk J ^a   Colinge, Jean Pierre ^a   Maes, Herman E ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORKS--EQUIVALENT CIRCUITS; SEMICONDUCTING FILMS--THIN FILMS; SEMICONDUCTOR DEVICE MANUFACTURE--SILICON ON INSULATOR TECHNOLOGY;

DOUBLE GATE CONTROL; SUBTHRESHOLD CONDUCTION;

SEMICONDUCTOR DEVICES, MOSFET;

EID: 0025482231     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.57165     Document Type: Article

References (16)

1. J-P. Colinge, “Subthreshold slope of thin-film SOI MOSFET’s,” IEEE Electron Device Lett., vol. EDL-7, no. 4, p. 244, 1986.
2. S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York, NY: Wiley, 1981, p. 447.
3. M. Y. Darwish, M. E. Roulet, and P. K. Schwob, “The subthreshold behavior of SOS MOST’s,” IEEE Trans. Electron Devices, vol. ED-25, p. 885, 1978.
4. E. R. Worley, “Theory of the fully depleted SOI/MOS transistor,” Solid State Electron., vol. 23, p. 1107, 1980.
5. F. Balestra and J. Brini, “Weak inversion and weak accumulation slope factors for deep depleted SOI MOSFET,” in Proc. 16th ESS-DERC Conf., (Cambridge, 1987) vol. 10G, p. 234. —, “SOI MOSFET in weak inversion and weak accumulation,” Electron. Lett., vol. 23, no. 5, p. 211, 1987.
6. J. R. Davis, A. E. Glaccum, K. Reeson, and P. L. F. Hemment, “Improved subthreshold characteristics of n-channel SOI transistors,” IEEE Electron Device Lett., vol. EDL-7, p. 570, 1986.
7. J. C. Sturm, “Performance advantages of submicron silicon-on-insulator devices for ULSI,” in Material Research Society Symp. Proc., vol. 107, p. 295, 1988.
8. E. R. Worley, “Weak inversion characteristics of the fully depleted SOS MOSFET,” IEEE Electron Device Lett., vol. EDL-2, p. 139, 1981.
9. D. J. Wouters, M. R. Tack, G. V. Groeseneken, H. E. Maes, and C. L. Claeys, “Characterization of front and back SiO2 interfaces in thick-and thin-film silicon-on-insulator MOS structures by the charge-pumping technique,” IEEE Trans. Electron Devices, vol. 36, p. 1746, 1989.
10. D. J. Foster, “Subthreshold currents in CMOS transistors made in oxygen-implanted silicon,” Electron. Lett., vol. 19, no. 17, p. 684, 1983.
11. R. J. Van Overstraeten, G. J. Declerck, and P. A. Muls, “Theory of the MOS transistor in weak inversion - new method to determine the number of surface traps,” IEEE Trans. Electron Devices, vol. ED-22, p. 282, 1975.
12. F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, “Double-gate silicon-on-insulator transitor with volume inversion: a new device with greatly enhanced performance,” IEEE Electron Device Lett., vol. EDL-8, p. 410, 1987. F. Balestra et al., “Analytical modelling of single and double gate thin film SOI MOSFETs,” in Proc. 19th ESSDERC. Berlin, Germany: Springer Verlag, 1989, p. 889.
13. R. J. Van Overstraeten, G. Declerck, and G. L. Broux, “Inadequacy of the classical theory of the MOS transistor operating in weak inversion,” IEEE Trans. Electron Devices, vol. ED-20, p. 1150, 1973.
14. H. K. Lim and J. G. Fossum, “Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-30, p. 1244, 1983.
15. H. Takato, K. Sunouchi, N. Okabe, A. Nitayama, K. Hieda, F. Horiguchi, and F. Masukoa, “High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs,” in IEDM Tech. Dig., p. 222, 1988.
16. D. Hisamoto, T. Kaga, Y. Kawamoto, and E. Takeda, “A fully depleted lean-channel transistor (DELTA)—A novel vertical ultra thin SOI MOSFET,” in IEDM Tech. Dig., p. 833, 1989.