Characterization of Bipolar Snapback and Breakdown Voltage in Thin-Film SOI Transistors by Two-Dimensional Simulation

IEEE Transactions on Electron Devices

Volumn 38, Issue 2, 1991, Pages 328-336

  Armstrong, G A ^a   Davis, J R ^b   Doyle, Aiden ^b  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

^b MARTLESHAM HEATH   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION--APPLICATIONS; HYSTERESIS; MATHEMATICAL TECHNIQUES--FINITE DIFFERENCE METHOD; SEMICONDUCTOR DEVICE MANUFACTURE--SILICON ON INSULATOR TECHNOLOGY; TRANSISTORS--THIN FILMS;

BIPOLAR SNAPBACK; BREAKDOWN VOLTAGE; FINITE DIFFERENCE SIMULATOR; SOI MOSFET'S; SUBMICROMETER DEVICES; ULTRATHIN FILM TRANSISTORS;

SEMICONDUCTOR DEVICES, MOSFET;

EID: 0026105337     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.69914     Document Type: Article

References (32)

1. S. D. S. Mahli, H. W. Lam, R. F. Pinizzotto, A. H. Hamdi, and F. D. McDaniel, “Novel SOI CMOS design using ultra thin near intrinsic substrate,” in IEDM Tech. Dig., pp. 107–110, 1982.
2. T. Sekigawa and Y. Hayashi, “Calculation of threshold voltage characteristics of an XMOS transistor having an additional bot tom gate,” Solid-State Electron., vol. 27, pp. 827–828, 1984.
3. J. P. Colinge, “Some properties of thin film SOI MOSFETs,” IEEE Circuits Devices Mag., vol. 3, pp. 16–20, 1987.
4. J. P. Colinge “Subthreshold slope of thin film SOI MOSFETs,” IEEE Electron Device Lett., vol. EDL-7, pp. 244–246, 1986.
5. M. Yoshimi, H. Hazama, M. Takahashi, S. Kambayashi, T. Wada, and H. Tango, “Simulation and experiments on high performance SOI MOSFETs made on a very thin film,” in 5th Int. FED 3D Workshop (Japan), pp. 113–118, 1988.
6. J. C. Sturm, K. Tokunaga, and J. P. Colinge, “Increased drain saturation current in ultra thin SOI transistors,” IEEE Electron Device Lett., vol. 9, pp. 460–463, 1988.
7. K. Kato, T. Wada, and K. Taniguchi, “Analysis of kink characteristics in silicon-on-insulator MOSFETs using two carrier modelling,” IEEE Trans. Electron Devices, vol. ED-32, pp. 458–465, 1985.
8. K. Kato and K. Taniguchi, “Numerical analysis of switching characteristics in SOI MOSFETs,” IEEE Trans. Electron Devices, vol. ED-33, pp. 133–139, 1986.
9. J. R. Davis, A. E. Glaccum, K. Reeson, and P. L. F. Hemment, “Improved subthreshold characteristics of n-channel SOI transistors,” IEEE Electron Device Lett., vol. EDL-7, pp. 570–573, 1986.
10. J. G. Fossum, R. Sundaresan, and M. Matloubian, “Anomalous subthreshold current-voltage characteristics of n-channel SOI MOSFETs,” IEEE Electron Device Lett., vol. EDL-8, pp. 544–546, 1987.
11. J. P. Colinge, “Reduction of floating substrate effect in thin film SOI MOSFETs,” Electron. Lett., vol. 22, p. 187, 1986.
12. M. Yoshimi, H. Hazama, M. Takahashi, S. Kambayashi, T. Wada, K. Kato, and H. Tango, “Two-dimensional simulation and measurement of high performance MOSFET’s made on very thin SOI film,” IEEE Trans. Electron Devices, vol. 36, no. 3, pp. 493–503, 1989.
13. K. K. Young and J. A. Burns, “Avalanche induced drain source breakdown in silicon-on-insulator n-MOSFETs,” IEEE Trans. Electron Devices, vol. 35, no. 4, pp. 426–431, 1988.
14. M. Yoshimi, “Design and application of ultrathin SOI MOS FETs,” in Proc IEEE SOS/SOI Technology Conf. (Nevada), pp. 145–146, 1989.
15. P. H. Woerlee, A. H. van Omnen, H. Lifka, C. A. H. Juffermans, L. Plaja, and F. M. Klassen, “Half-micron CMOS on ultra thin silicon on insulator,” in IEDM Tech. Dig., pp. 821–824, 1989.
16. C.-E. Chen, M. Matloubian, R. Sundaresan, B.-Y. Mao, C. C. Wei, and G. P. Pollack, “Single transistor latch in SOI MOS FETs,” IEEE Electron Device Lett., vol. 9, pp. 636–638, 1988.
17. A. J. Auberton-Herve, “SIMOX and VLSI high speed and radhard applications: discussion of body effect and circuit optimisation,” in Proc. IEEE SOS/SOI Technology Workshop (Georgia), p. 55, 1988.
18. L. J. McDaid, S. Hall, P. Mellor, W. Eccleston, and J. C. Alderman, “Physical origin of negative differential resistance in SOI transistors,” Electron. Lett., vol. 25, pp. 827–828, 1989.
19. G. A. Armstrong, N. J. Thomas, and J. R. Davis, “Characterisation of negative resistance and bipolar snapback in thin film SOI transistors by two-dimensional numerical simulation,” in Proc. IEEE SOS/SOI Technology Conf. (Nevada), pp. 44–45, 1989.
20. S. Selberherr, A. Schutz, and H. Potzl, “ A two-dimensional MOS transistor analyser,” IEEE Trans. Electron Devices, vol. ED-27, pp. 1540–1550, 1980.
21. A. Schutz, S. Selberherr, and H. Potzl, “Analysis of breakdown phenomena in MOSFET’s,” IEEE Trans. Computer-Aided Des., vol. CAD-1, pp. 77–85, 1982.
22. S. Selberherr, “The status of MINIMOS,” in Simulation of Semiconductor Devices and Processes, vol. 2, K. Board, Ed. White Plains, NY: Pineridge Press, 1986, pp. 2–15.
23. S. Selberherr, Analysis and Simulation of Semiconductor Devices. Vienna, Austria: Springer Verlag, 1984.
24. S. Selberherr “MOS device modeling at 77 K,” IEEE Trans. Electron Devices, vol. 36, pp. 1464–1474, 1989.
25. W. Hansch and S. Selberherr, “MINIMOS3: A MOSFET simulator that includes energy balance,” IEEE Trans. Electron Devices, vol. ED-34, 1074–1078, 1987.
26. J. W. Slotboom and G. Streuker, “The mobility model in MINIMOS,” in Proc. ESSDERC 89 (Berlin, Germany), pp. 87–90, 1989.
27. W. Shockley, “Problems related to p-n junctions in silicon,” Solid State Electron., vol. 2, pp. 35–56, 1961.
28. C. Werner, R. Kuhnert, and L. Risch, “Optimisation of lightly doped drain MOSFETs using a new quasi-ballistic simulation tool,” in IEDM Tech. Dig., pp. 770–773, 1984.
29. T. Thurgate and N. Chan, “An impact ionisation model for two dimensional device simulation,” IEEE Trans. Electron Devices, vol. ED-32, pp. 400–404, 1985.
30. M. Haond and J. P. Colinge, “Analysis of drain breakdown voltage in SOI n-channel MOSFETs,” Electron. Lett., vol. 25, pp. 1640–1641, 1989.
31. L. J. McDaid, S. Hall, W. Eccleston, and J. C. Alderman, “A simple technique for measuring the generation lifetime in SOI material using the principle of charge centroids,” to be published.
32. G. A. Armstrong and J. R. Davis, “Simulation of subthreshold characteristics of SOI MOSFETs,” in Proc. NASECODE V (Dublin, Ireland, 1987), pp. 115–123.