Examination of the time power law dependencies in hot carrier stressing of n-MOS transistors

IEEE Electron Device Letters

Volumn 18, Issue 2, 1997, Pages 51-53

  Doyle, B S ^a,b   Mistry, K R ^a   Faricelli, J ^a  

^a HEWLETT PACKARD COMPANY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC CHARGE; ELECTRONS; ELECTROSTATICS; HOT CARRIERS; MATHEMATICAL MODELS; OXIDES; SEMICONDUCTOR JUNCTIONS; STRESSES; TRANSCONDUCTANCE;

ELECTRONIC GATE CURRENT; MAXIMUM SUBSTRATE CURRENT; TRANSCONDUCTANCE DEGRADATION;

MOSFET DEVICES;

EID: 0031076015     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.553041     Document Type: Article

References (13)

1. E. Takeda and N. Suzuki, "An empirical model for device degradation due to hot-carrier injection," IEEE Electron Device Lett., vol. EDL-4, pp. 111-113, 1983.
2. C. Hu, S. C. Tam, F.-C. Hsu, P.-K. Ko, T.-Y. Chan, and K. W. Terrill, "Hot-electron-induced MOSFET degradation - Model, monitor, and improvement," IEEE Trans. Electron Devices, vol. ED-32, pp. 375-385, 1985.
3. d) during hot carrier stressing of n-MOS transistors," IEEE Trans. Electron Devices, vol. 37, pp. 744-755, 1990.
4. P. Bellens, P. Heremans, G. Groeseneken, and H. E. Maes, "Hot carrier effects in n-channel MOS transistors under alternate stress conditions," IEEE Electron Device Lett., vol. 9, pp. 232-234, 1988.
5. B. S. Doyle, M. Bourcerie, C. Bergonzoni, R. Benecci, A. Bravais, K. R. Mistry, and A. Boudou, "The generation and characterization of electron and hole traps created by hole injection during low gate voltage hot carrier stressing of n-MOS transistors," IEEE Trans. Electron Devices, vol. 37, pp. 1969-1877, 1990.
6. S. A. Kim, B. Menberu, T. E. Kopley, and J. E. Chung, "Oxide field dependence of the NMOS hot-carrier degradation rate and its impact on AC-lifetime prediction," in IEDM Tech. Dig., 1995, pp. 37-40.
7. N. S. Saks, P. L. Heremans, L. Van Den Hove, H. E. Maes, R. F. De Keersmaecker, and G. J. Declerck, "Observation of hot-hole injection in nMOS transistors using a modified floating-gate technique," IEEE Trans. Electron Devices, vol. ED-33, pp. 1529-1534, 1986.
8. B. S. Doyle, unpublished results.
9. B. S. Doyle and K. R. Mistry, "A lifetime prediction method for hot-carrier degradation in surface channel p-MOS devices," IEEE Trans. Electron Devices, vol. 37, pp. 301-307, 1990.
10. B. Doyle, J. Faricelli, K. Mistry, and D. Vuillaume, "Characterization of oxide trap and interface state creation during hot carrier stressing of n-MOS transistors using the floating gate technique," IEEE Electron Device Lett., vol. 14, pp. 63-65, 1993.
11. 2 interface," Appl. Phys. Lett., vol. 17, pp. 16-18, 1970.
12. M. H. White and J. R. Cricchi, "Characterization of thin-oxide MNOS memory transistors," IEEE Trans Electron Devices, vol. ED-19, p. 1280, 1972.
13. P. Heremans, R. Bellens, G. Groeseneken, and H. E. Maes, "Consistent model for the hot-carrier degradation in n-channel and p-channel MOSFET's," IEEE Trans. Electron Devices, vol. 35, pp. 2194-2209, 1988.