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Volumn 38, Issue 6, 1991, Pages 1289-1295

Properties of Ultra-Thin Wafer-Bonded Silicon-on-Insulator MOSFET’s

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR DEVICE MANUFACTURE - SILICON ON INSULATOR TECHNOLOGY; SEMICONDUCTOR MATERIALS - CHARGE CARRIERS;

EID: 0026169342     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.81619     Document Type: Article
Times cited : (57)

References (15)
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  • 2
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    • J. C. Sturm, K. Tokunga, and J-P. Colinge, “Increased drain saturation current in ultra-thin silicon-on-insulator (SOI) MOS transistors,” IEEE Electron Device Lett., vol. 9, pp. 460–463, 1988.
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  • 3
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    • Reduction of floating substrate effect in thin-film SOI MOSFET’s
    • J-P. Colinge, “Reduction of floating substrate effect in thin-film SOI MOSFET’s,” Electron. Lett., vol. 22, pp. 187–188, 1986.
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    • Colinge, J-P.1
  • 4
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    • Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET’s
    • H-K. Lim and J. C. Fossum, “Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-30, no. 10, pp. 1244–1251, 1983.
    • (1983) IEEE Trans. Electron Devices , vol.ED-30 , Issue.10 , pp. 1244-1251
    • Lim, H-K.1    Fossum, J.C.2
  • 5
    • 0025482231 scopus 로고
    • Subthreshold slope in thin-film SOI MOSFET’s
    • D. J. Wouters, J-P. Colinge, and H. E. Maes, “Subthreshold slope in thin-film SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 37, no. 9, pp. 1022–1033, 1990.
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  • 6
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    • Bonding of silicon wafers for silicon-on-insulator
    • W. P. Maszara, G. Goetz, A. Caviglia, and J. B. McKitterick, “Bonding of silicon wafers for silicon-on-insulator,” J. Appl. Phys., vol. 64, no. 10, pp. 4943-4950, 1988.
    • (1988) J. Appl. Phys. , vol.64 , Issue.10 , pp. 4943-4950
    • Maszara, W.P.1    Goetz, G.2    Caviglia, A.3    McKitterick, J.B.4
  • 7
    • 0023421993 scopus 로고
    • Double-gate silicon-on-insulator transistors with volume inversion: A new device with greatly enhanced performance
    • F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, “Double-gate silicon-on-insulator transistors with volume inversion: A new device with greatly enhanced performance,” IEEE Electron Device Lett., vol. EDL-8, pp. 410-412, 1987.
    • (1987) IEEE Electron Device Lett. , vol.EDL-8 , pp. 410-412
    • Balestra, F.1    Cristoloveanu, S.2    Benachir, M.3    Brini, J.4    Elewa, T.5
  • 8
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    • Analysis of conduction in fully depleted SOI MOSFET's
    • K. K. Young, “Analysis of conduction in fully depleted SOI MOSFET's,” IEEE Trans. Electron Devices, vol. 36, pp. 504-506, 1989.
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    • Young, K.K.1
  • 9
    • 0022149344 scopus 로고
    • Transconductance of silicon-on-insulator (SOI) MOS-FET's
    • J-P. Colinge, “Transconductance of silicon-on-insulator (SOI) MOS-FET's,” IEEE Electron Device Lett., vol. EDL-6, pp. 573-574, 1985.
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  • 10
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  • 11
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    • M. Matloubian, R. Sundaresan, and K. Lu, “Measurement and modeling of the sidewall threshold voltage of mesa-isolated SOI MOSFET's,” IEEE Trans. Electron Devices, vol. 36, pp. 938-942, 1989.
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    • Matloubian, M.1    Sundaresan, R.2    Lu, K.3
  • 12
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    • Deep depletion SOI MOSFET's with back potential control: A numerical simulation
    • F. Balestra, J. Brini, and P. Gentil, “Deep depletion SOI MOSFET's with back potential control: A numerical simulation,” Solid-State Electron., vol. 28, pp. 1031-1037, 1985.
    • (1985) Solid-State Electron. , vol.28 , pp. 1031-1037
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  • 13
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    • A dual-gate deep-depletion technique for generation lifetime measurements
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  • 15
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.