-
1
-
-
55449115308
-
Storage-class memory: The next storage system technology
-
Jul.
-
R. Freitas and W. Wilcke, "Storage-class memory: The next storage system technology, " IBM J. Res. Develop., vol. 52, nos. 4-5, pp. 439-447, Jul. 2008.
-
(2008)
IBM J. Res. Develop.
, vol.52
, Issue.4-5
, pp. 439-447
-
-
Freitas, R.1
Wilcke, W.2
-
2
-
-
55449122987
-
Overview of candidate device technologies for storage-class memory
-
Jul.
-
G. W. Burr et al., "Overview of candidate device technologies for storage-class memory, " IBM J. Res. Develop., vol. 52, nos. 4-5, pp. 449-464, Jul. 2008.
-
(2008)
IBM J. Res. Develop.
, vol.52
, Issue.4-5
, pp. 449-464
-
-
Burr, G.W.1
-
3
-
-
84905041584
-
Access devices for 3-D crosspoint memory
-
G. W. Burr et al., "Access devices for 3-D crosspoint memory, " J. Vac. Sci. Technol. B, vol. 32, no. 4, 2014, Art. ID 040802.
-
(2014)
J. Vac. Sci. Technol. B
, vol.32
, Issue.4
-
-
Burr, G.W.1
-
4
-
-
55349145969
-
2 as a resistive layer
-
Arlington, TX, USA
-
2 as a resistive layer, " in Proc. 8th IEEE Conf. Nanotechnol. (NANO), Arlington, TX, USA, 2008, pp. 319-322.
-
(2008)
Proc. 8th IEEE Conf. Nanotechnol. (NANO)
, pp. 319-322
-
-
Flocke, A.1
Noll, T.G.2
Kugeler, C.3
Nauenheim, C.4
Waser, R.5
-
5
-
-
77957010403
-
Cross-point memory array without cell selectors-Device characteristics and data storage pattern dependencies
-
Oct
-
J. Liang and H.-S. P. Wong, "Cross-point memory array without cell selectors-Device characteristics and data storage pattern dependencies, " IEEE Trans. Electron. Devices, vol. 57, no. 10, pp. 2531-2538, Oct. 2010.
-
(2010)
IEEE Trans. Electron. Devices
, vol.57
, Issue.10
, pp. 2531-2538
-
-
Liang, J.1
Wong, H.-S.P.2
-
6
-
-
84940115738
-
Synopsys
-
Synopsys. HSPICE. [Online]. Available: http://www.synopsys.com/tools/Verification/AMSVerification/CircuitSimulation/HSPICE/Pages/default.aspx
-
HSPICE
-
-
-
7
-
-
84940109174
-
-
Linear Technologies.
-
Linear Technologies. LTSPICE. [Online]. Available: http://www.linear.com/solutions/1066
-
LTSPICE
-
-
-
8
-
-
84875485846
-
A comprehensive crossbar array model with solutions for line resistance and nonlinear device characteristics
-
Apr
-
A. Chen, "A comprehensive crossbar array model with solutions for line resistance and nonlinear device characteristics, " IEEE Trans. Electron Devices, vol. 60, no. 4, pp. 1318-1326, Apr. 2013.
-
(2013)
IEEE Trans. Electron Devices
, vol.60
, Issue.4
, pp. 1318-1326
-
-
Chen, A.1
-
9
-
-
84906572350
-
Exploring the design space for resistive nonvolatile memory crossbar arrays with mixed-ionic-electronicconduction (MIEC)-based access devices
-
Santa Barbara, CA, USA
-
P. Narayanan et al., "Exploring the design space for resistive nonvolatile memory crossbar arrays with mixed-ionic-electronicconduction (MIEC)-based access devices, " in Proc. Device Res. Conf., Santa Barbara, CA, USA, 2014, pp. 239-240.
-
(2014)
Proc. Device Res. Conf.
, pp. 239-240
-
-
Narayanan, P.1
-
10
-
-
84907202556
-
MIEC (mixed-ionic-electronic-conduction)-based access devices for non-volatile crossbar memory arrays
-
R. S. Shenoy et al., "MIEC (mixed-ionic-electronic-conduction)-based access devices for non-volatile crossbar memory arrays, " Semicond. Sci. Technol., vol. 29, no. 10, 2014, Art. ID 104005.
-
(2014)
Semicond. Sci. Technol.
, vol.29
, Issue.10
-
-
Shenoy, R.S.1
-
11
-
-
77957871741
-
Highly-scalable novel access device based on mixed ionic electronic conduction (MIEC) materials for high density phase change memory (PCM) arrays
-
Honolulu, HI, USA
-
K. Gopalakrishnan et al., "Highly-scalable novel access device based on mixed ionic electronic conduction (MIEC) materials for high density phase change memory (PCM) arrays, " in Proc. Symp. VLSI Technol., Honolulu, HI, USA, 2010, pp. 205-206.
-
(2010)
Proc. Symp. VLSI Technol.
, pp. 205-206
-
-
Gopalakrishnan, K.1
-
12
-
-
80052672054
-
Endurance and scaling trends of novel access-devices for multi-layer crosspoint-memory based on mixed ionic electronic conduction (MIEC) materials
-
Honolulu, HI, USA
-
R. S. Shenoy et al., "Endurance and scaling trends of novel access-devices for multi-layer crosspoint-memory based on mixed ionic electronic conduction (MIEC) materials, " in Proc. Symp. VLSI Technol., Honolulu, HI, USA, 2011, pp. 94-95.
-
(2011)
Proc. Symp. VLSI Technol.
, pp. 94-95
-
-
Shenoy, R.S.1
-
13
-
-
84866552361
-
Large-scale (512kbit) integration of multilayerready access-devices based on mixed-ionic-electronic-conduction (MIEC) at 100% yield
-
Honolulu, HI, USA
-
G. W. Burr et al., "Large-scale (512kbit) integration of multilayerready access-devices based on mixed-ionic-electronic-conduction (MIEC) at 100% yield, " in Proc. Symp. VLSI Technol., Honolulu, HI, USA, 2012, pp. 41-42.
-
(2012)
Proc. Symp. VLSI Technol.
, pp. 41-42
-
-
Burr, G.W.1
-
14
-
-
84881539867
-
Sub-30nm scaling and high-speed operation of fully-confined access-devices for 3-D crosspoint memory based on mixed-ionic-electronic-conduction (MIEC) materials
-
San Francisco, CA, USA
-
K. Virwani et al., "Sub-30nm scaling and high-speed operation of fully-confined access-devices for 3-D crosspoint memory based on mixed-ionic-electronic-conduction (MIEC) materials, " in IEDM Tech. Dig., San Francisco, CA, USA, 2012, pp. 2.7.1-2.7.4.
-
(2012)
IEDM Tech. Dig.
, pp. 271-274
-
-
Virwani, K.1
-
15
-
-
84883405139
-
Recovery dynamics and fast (sub-50ns) read operation with access devices for 3D crosspoint memory based on mixed-ionic-electronic-conduction (MIEC)
-
Kyoto, Japan
-
G. W. Burr et al., "Recovery dynamics and fast (sub-50ns) read operation with access devices for 3D crosspoint memory based on mixed-ionic-electronic-conduction (MIEC), " in Proc. Symp. VLSI Technol., Kyoto, Japan, 2013, pp. T66-T67.
-
(2013)
Proc. Symp. VLSI Technol.
, pp. T66-T67
-
-
Burr, G.W.1
-
16
-
-
84938281754
-
Circuit-level benchmarking of access devices for resistive nonvolatile memory arrays
-
San Francisco, CA, USA
-
P. Narayanan, G. W. Burr, R. S. Shenoy, K. Virwani, and B. Kurdi, "Circuit-level benchmarking of access devices for resistive nonvolatile memory arrays, " in Proc. Int. Electron Devices Meeting, San Francisco, CA, USA, 2014, pp. 29.7.1-29.7.4.
-
(2014)
Proc. Int. Electron Devices Meeting
, pp. 2971-2974
-
-
Narayanan, P.1
Burr, G.W.2
Shenoy, R.S.3
Virwani, K.4
Kurdi, B.5
-
17
-
-
84856355683
-
Low power cross-point memory architecture
-
Jeju, Korea
-
B. Bateman, C. Siau, and C. Chevallier, "Low power cross-point memory architecture, " in Proc. IEEE Asian Solid State Circuits Conf. (A-SSCC), Jeju, Korea, 2011, pp. 173-176.
-
(2011)
Proc. IEEE Asian Solid State Circuits Conf. (A-SSCC)
, pp. 173-176
-
-
Bateman, B.1
Siau, C.2
Chevallier, C.3
-
18
-
-
84860664697
-
An 8Mb multi-layered cross-point ReRAM macro with 443MB/s write throughput
-
San Francisco, CA, USA
-
A. Kawahara et al., "An 8Mb multi-layered cross-point ReRAM macro with 443MB/s write throughput, " in Proc. ISSCC, San Francisco, CA, USA, 2012, pp. 432-434.
-
(2012)
Proc. ISSCC
, pp. 432-434
-
-
Kawahara, A.1
-
19
-
-
84872114992
-
An 8 Mb multi-layered cross-point ReRAM macro with 443 Mb/s write throughput
-
Jan
-
A. Kawahara et al., "An 8 Mb multi-layered cross-point ReRAM macro with 443 Mb/s write throughput, " IEEE J. Solid State Circuits, vol. 48, no. 1, pp. 178-185, Jan. 2013.
-
(2013)
IEEE J. Solid State Circuits
, vol.48
, Issue.1
, pp. 178-185
-
-
Kawahara, A.1
-
20
-
-
84876551262
-
A 130.7mm2 2-layer 32Gb ReRAM memory device in 24nm technology
-
San Francisco, CA, USA
-
T.-Y. Liu et al., "A 130.7mm2 2-layer 32Gb ReRAM memory device in 24nm technology, " in Proc. ISSCC, San Francisco, CA, USA, 2013, pp. 210-211.
-
(2013)
Proc. ISSCC
, pp. 210-211
-
-
Liu, T.-Y.1
-
22
-
-
84874861265
-
Effect of wordline/bitline scaling on the performance, energy consumption, and reliability of cross-point memory
-
J. L. Liang, S. Yeh, S. S. Wong, and H. S. P. Wong, "Effect of wordline/bitline scaling on the performance, energy consumption, and reliability of cross-point memory, " ACM J. Emerg. Technol. Comput. Syst., vol. 9, no. 1, pp. 9:1-9:14, 2013.
-
(2013)
ACM J. Emerg. Technol. Comput. Syst.
, vol.9
, Issue.1
, pp. 91-914
-
-
Liang, J.L.1
Yeh, S.2
Wong, S.S.3
Wong, H.S.P.4
-
23
-
-
84865536752
-
Design trade-offs for high density cross-point resistive memory
-
Redondo Beach, CA, USA
-
D. Niu, C. Xu, N. Muralimanohar, N. P. Jouppi, and Y. Xie, "Design trade-offs for high density cross-point resistive memory, " in Proc. ACM/IEEE Int. Symp. Low Power Electron. Design, Redondo Beach, CA, USA, 2012, pp. 209-214.
-
(2012)
Proc. ACM/IEEE Int. Symp. Low Power Electron. Design
, pp. 209-214
-
-
Niu, D.1
Xu, C.2
Muralimanohar, N.3
Jouppi, N.P.4
Xie, Y.5
-
24
-
-
84866561026
-
Dynamic 'hour glass' model for SET and RESET in HfO2 RRAM
-
Honolulu, HI, USA
-
R. Degraeve et al., "Dynamic 'hour glass' model for SET and RESET in HfO2 RRAM, " in Proc. Symp. VLSI Technol., Honolulu, HI, USA, 2012, pp. 75-76.
-
(2012)
Proc. Symp. VLSI Technol.
, pp. 75-76
-
-
Degraeve, R.1
-
25
-
-
84858976459
-
Accessibility of nano-crossbar arrays of resistive switching devices
-
Portland, OR, USA
-
A. Chen, "Accessibility of nano-crossbar arrays of resistive switching devices, " in Proc. 11th IEEE Conf. Nanotechnol. (IEEE-NANO), Portland, OR, USA, 2011, pp. 1767-1771.
-
(2011)
Proc. 11th IEEE Conf. Nanotechnol. (IEEE-NANO)
, pp. 1767-1771
-
-
Chen, A.1
-
26
-
-
44849117666
-
Fundamental analysis of resistive nanocrossbars for the use in hybrid nano/CMOS-memory
-
Munich, Germany
-
A. Flocke and T. G. Noll, "Fundamental analysis of resistive nanocrossbars for the use in hybrid nano/CMOS-memory, " in Proc. Eur. Solid State Circuits Conf. (ESSCIRC), Munich, Germany, 2007, pp. 328-331.
-
(2007)
Proc. Eur. Solid State Circuits Conf. (ESSCIRC)
, pp. 328-331
-
-
Flocke, A.1
Noll, T.G.2
-
27
-
-
77955646510
-
Size limitation of cross-point memory array and its dependence on data storage pattern and device parameters
-
Burlingame, CA, USA
-
J. Liang and H.-S. P. Wong, "Size limitation of cross-point memory array and its dependence on data storage pattern and device parameters, " in Proc. Int. Interconnect Technol. Conf. (IITC), Burlingame, CA, USA, 2010, pp. 1-3.
-
(2010)
Proc. Int. Interconnect Technol. Conf. (IITC)
, pp. 1-3
-
-
Liang, J.1
Wong, H.-S.P.2
-
28
-
-
84870610864
-
Analysis of the effect of cell parameters on the maximum RRAM array size considering both read and write
-
Bordeaux, France
-
L. Zhang, S. Cosemans, D. J. Wouters, G. Groeseneken, and M. Jurczak, "Analysis of the effect of cell parameters on the maximum RRAM array size considering both read and write, " in Proc. ESSDERC, Bordeaux, France, 2012, pp. 282-285.
-
(2012)
Proc. ESSDERC
, pp. 282-285
-
-
Zhang, L.1
Cosemans, S.2
Wouters, D.J.3
Groeseneken, G.4
Jurczak, M.5
-
29
-
-
84855772398
-
A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications
-
K. H. Kim et al., "A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications, " Nano Lett., vol. 12, no. 1, pp. 389-395, 2012.
-
(2012)
Nano Lett.
, vol.12
, Issue.1
, pp. 389-395
-
-
Kim, K.H.1
-
30
-
-
84866534688
-
Integration of 4F2 selector-less crossbar array 2Mb ReRAM based on transition metal oxides for high density memory applications
-
Honolulu, HI, USA
-
H. Lee et al., "Integration of 4F2 selector-less crossbar array 2Mb ReRAM based on transition metal oxides for high density memory applications, " in Proc. Symp. VLSI Technol., Honolulu, HI, USA, 2012, pp. 151-152.
-
(2012)
Proc. Symp. VLSI Technol.
, pp. 151-152
-
-
Lee, H.1
-
31
-
-
77952166363
-
A 0.13?m 64Mb multi-layered conductive metal-oxide memory
-
San Francisco, CA, USA
-
C. J. Chevallier et al., "A 0.13?m 64Mb multi-layered conductive metal-oxide memory, " in Proc. ISSCC, San Francisco, CA, USA, 2010, pp. 260-261.
-
(2010)
Proc. ISSCC
, pp. 260-261
-
-
Chevallier, C.J.1
-
32
-
-
77958553531
-
A theoretical model for Schottky diodes for excluding the sneak current in cross bar array resistive memory
-
G. H. Kim et al., "A theoretical model for Schottky diodes for excluding the sneak current in cross bar array resistive memory, " Nanotechnology, vol. 21, no. 38, 2010, Art. ID 385202.
-
(2010)
Nanotechnology
, vol.21
, Issue.38
-
-
Kim, G.H.1
-
33
-
-
84871799817
-
Dependence of read margin on pull-up schemes in high-density one selector-one resistor crossbar array
-
Jan
-
C. L. Lo, T. H. Hou, M. C. Chen, and J. J. Huang, "Dependence of read margin on pull-up schemes in high-density one selector-one resistor crossbar array, " IEEE Trans. Electron Devices, vol. 60, no. 1, pp. 420-426, Jan. 2013.
-
(2013)
IEEE Trans. Electron Devices
, vol.60
, Issue.1
, pp. 420-426
-
-
Lo, C.L.1
Hou, T.H.2
Chen, M.C.3
Huang, J.J.4
-
34
-
-
80053565784
-
Bipolar nonlinear Ni/TiO2/Ni selector for 1S1R crossbar array applications
-
Oct
-
J. J. Huang, Y. M. Tseng, C. W. Hsu, and T. H. Hou, "Bipolar nonlinear Ni/TiO2/Ni selector for 1S1R crossbar array applications, " IEEE Electron Device Lett., vol. 32, no. 10, pp. 1427-1429, Oct. 2011.
-
(2011)
IEEE Electron Device Lett.
, vol.32
, Issue.10
, pp. 1427-1429
-
-
Huang, J.J.1
Tseng, Y.M.2
Hsu, C.W.3
Hou, T.H.4
-
35
-
-
84881127090
-
On the potential of CRS, 1D1R, and 1S1R crossbar RRAM for storage-class memory
-
Hsinchu, Taiwan
-
C.-L. Lo, M.-C. Chen, J.-J. Huang, and T.-H. Hou, "On the potential of CRS, 1D1R, and 1S1R crossbar RRAM for storage-class memory, " in Proc. VLSI-TSA, Hsinchu, Taiwan, 2013, pp. 1-2.
-
(2013)
Proc. VLSI-TSA
, pp. 1-2
-
-
Lo, C.-L.1
Chen, M.-C.2
Huang, J.-J.3
Hou, T.-H.4
-
36
-
-
84872848395
-
RRAM crossbar array with cell selection device: A device and circuit interaction study
-
Feb
-
Y. X. Deng et al., "RRAM crossbar array with cell selection device: A device and circuit interaction study, " IEEE Trans. Electron Devices, vol. 60, no. 2, pp. 719-726, Feb. 2013.
-
(2013)
IEEE Trans. Electron Devices
, vol.60
, Issue.2
, pp. 719-726
-
-
Deng, Y.X.1
-
37
-
-
84899915056
-
Crossbar RRAM arrays: Selector device requirements during read operation
-
May
-
J. Zhou, K.-H. Kim, and W. Lu, "Crossbar RRAM arrays: Selector device requirements during read operation, " IEEE Trans. Electron Devices, vol. 61, no. 5, pp. 1369-1376, May 2014.
-
(2014)
IEEE Trans. Electron Devices
, vol.61
, Issue.5
, pp. 1369-1376
-
-
Zhou, J.1
Kim, K.-H.2
Lu, W.3
-
38
-
-
84862832207
-
An ultra-low reset current cross-point phase change memory with carbon nanotube electrodes
-
Apr
-
J. L. Liang, R. G. D. Jeyasingh, H. Y. Chen, and H. S. P. Wong, "An ultra-low reset current cross-point phase change memory with carbon nanotube electrodes, " IEEE Trans. Electron Devices, vol. 59, no. 4, pp. 1155-1163, Apr. 2012.
-
(2012)
IEEE Trans. Electron Devices
, vol.59
, Issue.4
, pp. 1155-1163
-
-
Liang, J.L.1
Jeyasingh, R.G.D.2
Chen, H.Y.3
Wong, H.S.P.4
-
39
-
-
84884688425
-
The impact of n-p-n selector based bipolar RRAM cross-point on array performance
-
Oct
-
R. Mandapati et al., "The impact of n-p-n selector based bipolar RRAM cross-point on array performance, " IEEE Trans. Electron Devices, vol. 60, no. 10, pp. 3385-3392, Oct. 2013.
-
(2013)
IEEE Trans. Electron Devices
, vol.60
, Issue.10
, pp. 3385-3392
-
-
Mandapati, R.1
-
40
-
-
84904654989
-
Selector design considerations and requirements for 1S1R RRAM crossbar array
-
Taipei, Taiwan, May
-
L. Zhang et al., "Selector design considerations and requirements for 1S1R RRAM crossbar array, " in Proc. IEEE 6th Int. Memory Workshop (IMW), Taipei, Taiwan, May 2014, pp. 1-4.
-
(2014)
Proc. IEEE 6th Int. Memory Workshop (IMW)
, pp. 1-4
-
-
Zhang, L.1
|