Design trade-offs for high density cross-point resistive memory

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2012, Pages 209-214

  Niu, Dimin ^a   Xu, Cong ^a   Muralimanohar, Naveen ^b   Jouppi, Norman P ^b   Xie, Yuan ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

cross point array; non volatile memory; resistive memory

Indexed keywords

3D STACKING; AREA OVERHEAD; CELL PARAMETER; CELL SIZE; COMPREHENSIVE ANALYSIS; CONVENTIONAL MEMORIES; CROSS-POINT ARRAY; DESIGN CHALLENGES; DESIGN STAGE; DESIGN TRADEOFF; DEVICE CHARACTERISTICS; FEATURE SIZES; HIGH DENSITY; MEMORY DENSITY; MEMORY TECHNOLOGY; NON-VOLATILE MEMORIES; RESISTIVE MEMORIES; RESISTIVE RAMS; SCALING LIMITS; SINGLE LEVEL; SPECIFIC DESIGN;

CELLS; CYTOLOGY; DESIGN; ENERGY UTILIZATION; FEEDBACK CONTROL; LOW POWER ELECTRONICS; RELIABILITY ANALYSIS;

RANDOM ACCESS STORAGE;

EID: 84865536752     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2333660.2333712     Document Type: Conference Paper

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