A 130.7mm2 2-layer 32Gb ReRAM memory device in 24nm technology

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 56, Issue , 2013, Pages 210-211

  Liu, Tz Yi ^a   Yan, Tian Hong ^a   Scheuerlein, Roy ^a   Chen, Yingchang ^a   Lee, Jeffrey Koonyee ^a   Balakrishnan, Gopinath ^a   Yee, Gordon ^a   Zhang, Henry ^a   Yap, Alex ^a   Ouyang, Jingwen ^a   Sasaki, Takahiko ^b   Addepalli, Sravanti ^a   Al Shamma, Ali ^a   Chen, Chin Yu ^a   Gupta, Mayank ^a   Hilton, Greg ^a   Joshi, Saurabh ^a   Kathuria, Achal ^a   Lai, Vincent ^a   Masiwal, Deep ^a   Matsumoto, Masahide ^a   Nigam, Anurag ^a   Pai, Anil ^a   Pakhale, Jayesh ^a   Siau, Chang Hua ^a   Wu, Xiaoxia ^a   Yin, Ronald ^a   Peng, Liping ^a   Kang, Jang Yong ^a   Huynh, Sharon ^a   Wang, Huijuan ^a   Nagel, Nicolas ^a   Tanaka, Yoichiro ^a   Higashitani, Masaaki ^a   Minvielle, Tim ^a   Gorla, Chandu ^a   Tsukamoto, Takayuki ^b   Yamaguchi, Takeshi ^b   Okajima, Mutsumi ^b   Okamura, Takayuki ^b   Takase, Satoru ^b   Hara, Takahiko ^b   Inoue, Hirofumi ^b   Fasoli, Luca ^a   Mofidi, Mehrdad ^a   Shrivastava, Ritu ^a   Quader, Khandker ^a   more..

^a SanDisk Corporation   (United States)

^b TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH RELIABILITY; MEMORY MACRO; NON-VOLATILE MEMORY; POTENTIAL TECHNOLOGIES; TEST CHIPS;

NANOTECHNOLOGY;

EID: 84876551262     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2013.6487703     Document Type: Conference Paper

References (7)

1. M. Crowley et al., "512Mb PROM with 8 Layers of Antifuses/Diode Cells", ISSCC Dig. Tech. Papers, pp. 284-285, Feb. 2003.
2. A. Kawahara, et al., "An 8Mb Multi-Layered Cross-Point ReRAM Macro with 443MB/s Write Throughput", ISSCC Dig. Tech. Papers, pp. 432-433, Feb. 2012.
3. C. J. Chevallier, et al., "A 0.13μm 64Mb Multi-Layered Conductive Metal-Oxide Memory", ISSCC Dig. Tech. Papers, pp. 260-261, Feb. 2010.
4. R. E. Scheuerlein, "Word line arrangement having multi-layer word line segments for three-dimensional memory array", US Pat. 6 879 505, Apr. 2005.
5. T. Yan et al., "Three Dimensional Memory System with Column Pipeline", US Pub 2012-0224408, Sep. 2012.
6. G. Palumbo, et al., "Charge-Pump Circuits: Power-Consumption Optimization", IEEE Trans Circuit Syst.-I, Vol. 49, pp. 1535-1542, Nov. 2002.
7. M. Cazzaniga and T. Liu, "Charge Pump System that Dynamically Selects Number of Active Stages", US Pub 2012-0154022, Jun. 2012.